364 lines
8.2 KiB
C
364 lines
8.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA Management Engine (FME)
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include <linux/fpga-dfl.h>
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#include "dfl.h"
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#include "dfl-fme.h"
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static ssize_t ports_num_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
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v = readq(base + FME_HDR_CAP);
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return scnprintf(buf, PAGE_SIZE, "%u\n",
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(unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));
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}
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static DEVICE_ATTR_RO(ports_num);
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/*
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* Bitstream (static FPGA region) identifier number. It contains the
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* detailed version and other information of this static FPGA region.
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*/
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static ssize_t bitstream_id_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
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v = readq(base + FME_HDR_BITSTREAM_ID);
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return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
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}
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static DEVICE_ATTR_RO(bitstream_id);
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/*
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* Bitstream (static FPGA region) meta data. It contains the synthesis
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* date, seed and other information of this static FPGA region.
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*/
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static ssize_t bitstream_metadata_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
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v = readq(base + FME_HDR_BITSTREAM_MD);
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return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
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}
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static DEVICE_ATTR_RO(bitstream_metadata);
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static ssize_t cache_size_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
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v = readq(base + FME_HDR_CAP);
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return sprintf(buf, "%u\n",
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(unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));
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}
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static DEVICE_ATTR_RO(cache_size);
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static ssize_t fabric_version_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
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v = readq(base + FME_HDR_CAP);
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return sprintf(buf, "%u\n",
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(unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));
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}
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static DEVICE_ATTR_RO(fabric_version);
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static ssize_t socket_id_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
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v = readq(base + FME_HDR_CAP);
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return sprintf(buf, "%u\n",
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(unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));
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}
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static DEVICE_ATTR_RO(socket_id);
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static struct attribute *fme_hdr_attrs[] = {
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&dev_attr_ports_num.attr,
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&dev_attr_bitstream_id.attr,
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&dev_attr_bitstream_metadata.attr,
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&dev_attr_cache_size.attr,
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&dev_attr_fabric_version.attr,
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&dev_attr_socket_id.attr,
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NULL,
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};
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static const struct attribute_group fme_hdr_group = {
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.attrs = fme_hdr_attrs,
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};
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static long fme_hdr_ioctl_release_port(struct dfl_feature_platform_data *pdata,
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unsigned long arg)
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{
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struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
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int port_id;
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if (get_user(port_id, (int __user *)arg))
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return -EFAULT;
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return dfl_fpga_cdev_release_port(cdev, port_id);
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}
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static long fme_hdr_ioctl_assign_port(struct dfl_feature_platform_data *pdata,
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unsigned long arg)
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{
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struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
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int port_id;
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if (get_user(port_id, (int __user *)arg))
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return -EFAULT;
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return dfl_fpga_cdev_assign_port(cdev, port_id);
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}
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static long fme_hdr_ioctl(struct platform_device *pdev,
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struct dfl_feature *feature,
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unsigned int cmd, unsigned long arg)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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switch (cmd) {
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case DFL_FPGA_FME_PORT_RELEASE:
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return fme_hdr_ioctl_release_port(pdata, arg);
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case DFL_FPGA_FME_PORT_ASSIGN:
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return fme_hdr_ioctl_assign_port(pdata, arg);
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}
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return -ENODEV;
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}
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static const struct dfl_feature_id fme_hdr_id_table[] = {
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{.id = FME_FEATURE_ID_HEADER,},
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{0,}
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};
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static const struct dfl_feature_ops fme_hdr_ops = {
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.ioctl = fme_hdr_ioctl,
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};
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static struct dfl_feature_driver fme_feature_drvs[] = {
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{
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.id_table = fme_hdr_id_table,
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.ops = &fme_hdr_ops,
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},
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{
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.id_table = fme_pr_mgmt_id_table,
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.ops = &fme_pr_mgmt_ops,
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},
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{
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.id_table = fme_global_err_id_table,
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.ops = &fme_global_err_ops,
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},
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{
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.ops = NULL,
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},
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};
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static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
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unsigned long arg)
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{
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/* No extension support for now */
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return 0;
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}
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static int fme_open(struct inode *inode, struct file *filp)
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{
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struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev);
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int ret;
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if (WARN_ON(!pdata))
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return -ENODEV;
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ret = dfl_feature_dev_use_begin(pdata);
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if (ret)
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return ret;
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dev_dbg(&fdev->dev, "Device File Open\n");
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filp->private_data = pdata;
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return 0;
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}
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static int fme_release(struct inode *inode, struct file *filp)
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{
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struct dfl_feature_platform_data *pdata = filp->private_data;
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struct platform_device *pdev = pdata->dev;
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dev_dbg(&pdev->dev, "Device File Release\n");
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dfl_feature_dev_use_end(pdata);
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return 0;
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}
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static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
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{
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struct dfl_feature_platform_data *pdata = filp->private_data;
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struct platform_device *pdev = pdata->dev;
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struct dfl_feature *f;
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long ret;
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dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
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switch (cmd) {
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case DFL_FPGA_GET_API_VERSION:
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return DFL_FPGA_API_VERSION;
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case DFL_FPGA_CHECK_EXTENSION:
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return fme_ioctl_check_extension(pdata, arg);
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default:
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/*
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* Let sub-feature's ioctl function to handle the cmd.
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* Sub-feature's ioctl returns -ENODEV when cmd is not
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* handled in this sub feature, and returns 0 or other
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* error code if cmd is handled.
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*/
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dfl_fpga_dev_for_each_feature(pdata, f) {
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if (f->ops && f->ops->ioctl) {
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ret = f->ops->ioctl(pdev, f, cmd, arg);
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if (ret != -ENODEV)
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return ret;
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}
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}
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}
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return -EINVAL;
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}
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static int fme_dev_init(struct platform_device *pdev)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct dfl_fme *fme;
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fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL);
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if (!fme)
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return -ENOMEM;
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fme->pdata = pdata;
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mutex_lock(&pdata->lock);
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dfl_fpga_pdata_set_private(pdata, fme);
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mutex_unlock(&pdata->lock);
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return 0;
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}
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static void fme_dev_destroy(struct platform_device *pdev)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct dfl_fme *fme;
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mutex_lock(&pdata->lock);
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fme = dfl_fpga_pdata_get_private(pdata);
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dfl_fpga_pdata_set_private(pdata, NULL);
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mutex_unlock(&pdata->lock);
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}
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static const struct file_operations fme_fops = {
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.owner = THIS_MODULE,
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.open = fme_open,
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.release = fme_release,
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.unlocked_ioctl = fme_ioctl,
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};
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static int fme_probe(struct platform_device *pdev)
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{
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int ret;
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ret = fme_dev_init(pdev);
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if (ret)
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goto exit;
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ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
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if (ret)
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goto dev_destroy;
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ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
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if (ret)
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goto feature_uinit;
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return 0;
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feature_uinit:
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dfl_fpga_dev_feature_uinit(pdev);
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dev_destroy:
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fme_dev_destroy(pdev);
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exit:
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return ret;
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}
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static int fme_remove(struct platform_device *pdev)
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{
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dfl_fpga_dev_ops_unregister(pdev);
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dfl_fpga_dev_feature_uinit(pdev);
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fme_dev_destroy(pdev);
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return 0;
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}
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static const struct attribute_group *fme_dev_groups[] = {
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&fme_hdr_group,
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&fme_global_err_group,
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NULL
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};
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static struct platform_driver fme_driver = {
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.driver = {
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.name = DFL_FPGA_FEATURE_DEV_FME,
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.dev_groups = fme_dev_groups,
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},
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.probe = fme_probe,
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.remove = fme_remove,
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};
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module_platform_driver(fme_driver);
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MODULE_DESCRIPTION("FPGA Management Engine driver");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dfl-fme");
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