598 lines
14 KiB
C
598 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/aer.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include "nitrox_dev.h"
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#include "nitrox_common.h"
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#include "nitrox_csr.h"
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#include "nitrox_hal.h"
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#include "nitrox_isr.h"
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#include "nitrox_debugfs.h"
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#define CNN55XX_DEV_ID 0x12
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#define UCODE_HLEN 48
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#define DEFAULT_SE_GROUP 0
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#define DEFAULT_AE_GROUP 0
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#define DRIVER_VERSION "1.2"
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#define CNN55XX_UCD_BLOCK_SIZE 32768
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#define CNN55XX_MAX_UCODE_SIZE (CNN55XX_UCD_BLOCK_SIZE * 2)
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#define FW_DIR "cavium/"
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/* SE microcode */
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#define SE_FW FW_DIR "cnn55xx_se.fw"
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/* AE microcode */
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#define AE_FW FW_DIR "cnn55xx_ae.fw"
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static const char nitrox_driver_name[] = "CNN55XX";
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static LIST_HEAD(ndevlist);
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static DEFINE_MUTEX(devlist_lock);
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static unsigned int num_devices;
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/**
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* nitrox_pci_tbl - PCI Device ID Table
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*/
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static const struct pci_device_id nitrox_pci_tbl[] = {
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{PCI_VDEVICE(CAVIUM, CNN55XX_DEV_ID), 0},
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/* required last entry */
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{0, }
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};
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MODULE_DEVICE_TABLE(pci, nitrox_pci_tbl);
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static unsigned int qlen = DEFAULT_CMD_QLEN;
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module_param(qlen, uint, 0644);
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MODULE_PARM_DESC(qlen, "Command queue length - default 2048");
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#ifdef CONFIG_PCI_IOV
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int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs);
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#else
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int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs)
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{
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return 0;
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}
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#endif
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/**
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* struct ucode - Firmware Header
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* @id: microcode ID
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* @version: firmware version
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* @code_size: code section size
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* @raz: alignment
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* @code: code section
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*/
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struct ucode {
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u8 id;
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char version[VERSION_LEN - 1];
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__be32 code_size;
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u8 raz[12];
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u64 code[0];
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};
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/**
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* write_to_ucd_unit - Write Firmware to NITROX UCD unit
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*/
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static void write_to_ucd_unit(struct nitrox_device *ndev, u32 ucode_size,
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u64 *ucode_data, int block_num)
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{
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u32 code_size;
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u64 offset, data;
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int i = 0;
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/*
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* UCD structure
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*
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* -------------
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* | BLK 7 |
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* -------------
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* | BLK 6 |
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* -------------
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* | ... |
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* -------------
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* | BLK 0 |
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* -------------
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* Total of 8 blocks, each size 32KB
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*/
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/* set the block number */
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offset = UCD_UCODE_LOAD_BLOCK_NUM;
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nitrox_write_csr(ndev, offset, block_num);
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code_size = roundup(ucode_size, 16);
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while (code_size) {
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data = ucode_data[i];
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/* write 8 bytes at a time */
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offset = UCD_UCODE_LOAD_IDX_DATAX(i);
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nitrox_write_csr(ndev, offset, data);
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code_size -= 8;
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i++;
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}
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usleep_range(300, 400);
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}
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static int nitrox_load_fw(struct nitrox_device *ndev)
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{
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const struct firmware *fw;
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const char *fw_name;
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struct ucode *ucode;
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u64 *ucode_data;
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u64 offset;
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union ucd_core_eid_ucode_block_num core_2_eid_val;
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union aqm_grp_execmsk_lo aqm_grp_execmask_lo;
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union aqm_grp_execmsk_hi aqm_grp_execmask_hi;
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u32 ucode_size;
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int ret, i = 0;
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fw_name = SE_FW;
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dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
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ret = request_firmware(&fw, fw_name, DEV(ndev));
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if (ret < 0) {
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dev_err(DEV(ndev), "failed to get firmware %s\n", fw_name);
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return ret;
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}
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ucode = (struct ucode *)fw->data;
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ucode_size = be32_to_cpu(ucode->code_size) * 2;
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if (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {
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dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n",
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ucode_size, fw_name);
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release_firmware(fw);
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return -EINVAL;
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}
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ucode_data = ucode->code;
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/* copy the firmware version */
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memcpy(&ndev->hw.fw_name[0][0], ucode->version, (VERSION_LEN - 2));
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ndev->hw.fw_name[0][VERSION_LEN - 1] = '\0';
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/* Load SE Firmware on UCD Block 0 */
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write_to_ucd_unit(ndev, ucode_size, ucode_data, 0);
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release_firmware(fw);
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/* put all SE cores in DEFAULT_SE_GROUP */
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offset = POM_GRP_EXECMASKX(DEFAULT_SE_GROUP);
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nitrox_write_csr(ndev, offset, (~0ULL));
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/* write block number and firmware length
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* bit:<2:0> block number
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* bit:3 is set SE uses 32KB microcode
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* bit:3 is clear SE uses 64KB microcode
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*/
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core_2_eid_val.value = 0ULL;
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core_2_eid_val.ucode_blk = 0;
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if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
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core_2_eid_val.ucode_len = 1;
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else
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core_2_eid_val.ucode_len = 0;
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for (i = 0; i < ndev->hw.se_cores; i++) {
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offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
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nitrox_write_csr(ndev, offset, core_2_eid_val.value);
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}
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fw_name = AE_FW;
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dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
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ret = request_firmware(&fw, fw_name, DEV(ndev));
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if (ret < 0) {
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dev_err(DEV(ndev), "failed to get firmware %s\n", fw_name);
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return ret;
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}
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ucode = (struct ucode *)fw->data;
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ucode_size = be32_to_cpu(ucode->code_size) * 2;
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if (!ucode_size || ucode_size > CNN55XX_MAX_UCODE_SIZE) {
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dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n",
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ucode_size, fw_name);
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release_firmware(fw);
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return -EINVAL;
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}
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ucode_data = ucode->code;
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/* copy the firmware version */
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memcpy(&ndev->hw.fw_name[1][0], ucode->version, (VERSION_LEN - 2));
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ndev->hw.fw_name[1][VERSION_LEN - 1] = '\0';
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/* Load AE Firmware on UCD Block 2 */
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write_to_ucd_unit(ndev, ucode_size, ucode_data, 2);
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release_firmware(fw);
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/* put all AE cores in DEFAULT_AE_GROUP */
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offset = AQM_GRP_EXECMSK_LOX(DEFAULT_AE_GROUP);
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aqm_grp_execmask_lo.exec_0_to_39 = 0xFFFFFFFFFFULL;
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nitrox_write_csr(ndev, offset, aqm_grp_execmask_lo.value);
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offset = AQM_GRP_EXECMSK_HIX(DEFAULT_AE_GROUP);
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aqm_grp_execmask_hi.exec_40_to_79 = 0xFFFFFFFFFFULL;
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nitrox_write_csr(ndev, offset, aqm_grp_execmask_hi.value);
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/* write block number and firmware length
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* bit:<2:0> block number
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* bit:3 is set AE uses 32KB microcode
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* bit:3 is clear AE uses 64KB microcode
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*/
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core_2_eid_val.value = 0ULL;
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core_2_eid_val.ucode_blk = 2;
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if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
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core_2_eid_val.ucode_len = 1;
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else
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core_2_eid_val.ucode_len = 0;
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for (i = 0; i < ndev->hw.ae_cores; i++) {
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offset = UCD_AE_EID_UCODE_BLOCK_NUMX(i);
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nitrox_write_csr(ndev, offset, core_2_eid_val.value);
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}
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return 0;
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}
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/**
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* nitrox_add_to_devlist - add NITROX device to global device list
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* @ndev: NITROX device
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*/
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static int nitrox_add_to_devlist(struct nitrox_device *ndev)
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{
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struct nitrox_device *dev;
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int ret = 0;
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INIT_LIST_HEAD(&ndev->list);
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refcount_set(&ndev->refcnt, 1);
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mutex_lock(&devlist_lock);
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list_for_each_entry(dev, &ndevlist, list) {
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if (dev == ndev) {
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ret = -EEXIST;
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goto unlock;
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}
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}
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ndev->idx = num_devices++;
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list_add_tail(&ndev->list, &ndevlist);
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unlock:
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mutex_unlock(&devlist_lock);
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return ret;
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}
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/**
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* nitrox_remove_from_devlist - remove NITROX device from
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* global device list
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* @ndev: NITROX device
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*/
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static void nitrox_remove_from_devlist(struct nitrox_device *ndev)
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{
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mutex_lock(&devlist_lock);
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list_del(&ndev->list);
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num_devices--;
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mutex_unlock(&devlist_lock);
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}
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struct nitrox_device *nitrox_get_first_device(void)
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{
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struct nitrox_device *ndev = NULL;
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mutex_lock(&devlist_lock);
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list_for_each_entry(ndev, &ndevlist, list) {
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if (nitrox_ready(ndev))
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break;
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}
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mutex_unlock(&devlist_lock);
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if (!ndev)
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return NULL;
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refcount_inc(&ndev->refcnt);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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return ndev;
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}
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void nitrox_put_device(struct nitrox_device *ndev)
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{
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if (!ndev)
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return;
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refcount_dec(&ndev->refcnt);
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/* barrier to sync with other cpus */
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smp_mb__after_atomic();
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}
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static int nitrox_device_flr(struct pci_dev *pdev)
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{
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int pos = 0;
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pos = pci_save_state(pdev);
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if (pos) {
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dev_err(&pdev->dev, "Failed to save pci state\n");
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return -ENOMEM;
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}
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/* check flr support */
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if (pcie_has_flr(pdev))
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pcie_flr(pdev);
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pci_restore_state(pdev);
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return 0;
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}
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static int nitrox_pf_sw_init(struct nitrox_device *ndev)
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{
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int err;
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err = nitrox_common_sw_init(ndev);
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if (err)
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return err;
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err = nitrox_register_interrupts(ndev);
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if (err)
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nitrox_common_sw_cleanup(ndev);
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return err;
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}
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static void nitrox_pf_sw_cleanup(struct nitrox_device *ndev)
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{
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nitrox_unregister_interrupts(ndev);
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nitrox_common_sw_cleanup(ndev);
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}
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/**
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* nitrox_bist_check - Check NITORX BIST registers status
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* @ndev: NITROX device
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*/
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static int nitrox_bist_check(struct nitrox_device *ndev)
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{
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u64 value = 0;
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int i;
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for (i = 0; i < NR_CLUSTERS; i++) {
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value += nitrox_read_csr(ndev, EMU_BIST_STATUSX(i));
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value += nitrox_read_csr(ndev, EFL_CORE_BIST_REGX(i));
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}
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value += nitrox_read_csr(ndev, UCD_BIST_STATUS);
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value += nitrox_read_csr(ndev, NPS_CORE_BIST_REG);
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value += nitrox_read_csr(ndev, NPS_CORE_NPC_BIST_REG);
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value += nitrox_read_csr(ndev, NPS_PKT_SLC_BIST_REG);
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value += nitrox_read_csr(ndev, NPS_PKT_IN_BIST_REG);
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value += nitrox_read_csr(ndev, POM_BIST_REG);
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value += nitrox_read_csr(ndev, BMI_BIST_REG);
|
||
|
|
value += nitrox_read_csr(ndev, EFL_TOP_BIST_STAT);
|
||
|
|
value += nitrox_read_csr(ndev, BMO_BIST_REG);
|
||
|
|
value += nitrox_read_csr(ndev, LBC_BIST_STATUS);
|
||
|
|
value += nitrox_read_csr(ndev, PEM_BIST_STATUSX(0));
|
||
|
|
if (value)
|
||
|
|
return -EIO;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int nitrox_pf_hw_init(struct nitrox_device *ndev)
|
||
|
|
{
|
||
|
|
int err;
|
||
|
|
|
||
|
|
err = nitrox_bist_check(ndev);
|
||
|
|
if (err) {
|
||
|
|
dev_err(&ndev->pdev->dev, "BIST check failed\n");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
/* get cores information */
|
||
|
|
nitrox_get_hwinfo(ndev);
|
||
|
|
|
||
|
|
nitrox_config_nps_core_unit(ndev);
|
||
|
|
nitrox_config_aqm_unit(ndev);
|
||
|
|
nitrox_config_nps_pkt_unit(ndev);
|
||
|
|
nitrox_config_pom_unit(ndev);
|
||
|
|
nitrox_config_efl_unit(ndev);
|
||
|
|
/* configure IO units */
|
||
|
|
nitrox_config_bmi_unit(ndev);
|
||
|
|
nitrox_config_bmo_unit(ndev);
|
||
|
|
/* configure Local Buffer Cache */
|
||
|
|
nitrox_config_lbc_unit(ndev);
|
||
|
|
nitrox_config_rand_unit(ndev);
|
||
|
|
|
||
|
|
/* load firmware on cores */
|
||
|
|
err = nitrox_load_fw(ndev);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
nitrox_config_emu_unit(ndev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* nitrox_probe - NITROX Initialization function.
|
||
|
|
* @pdev: PCI device information struct
|
||
|
|
* @id: entry in nitrox_pci_tbl
|
||
|
|
*
|
||
|
|
* Return: 0, if the driver is bound to the device, or
|
||
|
|
* a negative error if there is failure.
|
||
|
|
*/
|
||
|
|
static int nitrox_probe(struct pci_dev *pdev,
|
||
|
|
const struct pci_device_id *id)
|
||
|
|
{
|
||
|
|
struct nitrox_device *ndev;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
dev_info_once(&pdev->dev, "%s driver version %s\n",
|
||
|
|
nitrox_driver_name, DRIVER_VERSION);
|
||
|
|
|
||
|
|
err = pci_enable_device_mem(pdev);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
/* do FLR */
|
||
|
|
err = nitrox_device_flr(pdev);
|
||
|
|
if (err) {
|
||
|
|
dev_err(&pdev->dev, "FLR failed\n");
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
|
||
|
|
dev_dbg(&pdev->dev, "DMA to 64-BIT address\n");
|
||
|
|
} else {
|
||
|
|
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||
|
|
if (err) {
|
||
|
|
dev_err(&pdev->dev, "DMA configuration failed\n");
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
err = pci_request_mem_regions(pdev, nitrox_driver_name);
|
||
|
|
if (err) {
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
pci_set_master(pdev);
|
||
|
|
|
||
|
|
ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
|
||
|
|
if (!ndev) {
|
||
|
|
err = -ENOMEM;
|
||
|
|
goto ndev_fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
pci_set_drvdata(pdev, ndev);
|
||
|
|
ndev->pdev = pdev;
|
||
|
|
|
||
|
|
/* add to device list */
|
||
|
|
nitrox_add_to_devlist(ndev);
|
||
|
|
|
||
|
|
ndev->hw.vendor_id = pdev->vendor;
|
||
|
|
ndev->hw.device_id = pdev->device;
|
||
|
|
ndev->hw.revision_id = pdev->revision;
|
||
|
|
/* command timeout in jiffies */
|
||
|
|
ndev->timeout = msecs_to_jiffies(CMD_TIMEOUT);
|
||
|
|
ndev->node = dev_to_node(&pdev->dev);
|
||
|
|
if (ndev->node == NUMA_NO_NODE)
|
||
|
|
ndev->node = 0;
|
||
|
|
|
||
|
|
ndev->bar_addr = ioremap(pci_resource_start(pdev, 0),
|
||
|
|
pci_resource_len(pdev, 0));
|
||
|
|
if (!ndev->bar_addr) {
|
||
|
|
err = -EIO;
|
||
|
|
goto ioremap_err;
|
||
|
|
}
|
||
|
|
/* allocate command queus based on cpus, max queues are 64 */
|
||
|
|
ndev->nr_queues = min_t(u32, MAX_PF_QUEUES, num_online_cpus());
|
||
|
|
ndev->qlen = qlen;
|
||
|
|
|
||
|
|
err = nitrox_pf_sw_init(ndev);
|
||
|
|
if (err)
|
||
|
|
goto ioremap_err;
|
||
|
|
|
||
|
|
err = nitrox_pf_hw_init(ndev);
|
||
|
|
if (err)
|
||
|
|
goto pf_hw_fail;
|
||
|
|
|
||
|
|
nitrox_debugfs_init(ndev);
|
||
|
|
|
||
|
|
/* clear the statistics */
|
||
|
|
atomic64_set(&ndev->stats.posted, 0);
|
||
|
|
atomic64_set(&ndev->stats.completed, 0);
|
||
|
|
atomic64_set(&ndev->stats.dropped, 0);
|
||
|
|
|
||
|
|
atomic_set(&ndev->state, __NDEV_READY);
|
||
|
|
/* barrier to sync with other cpus */
|
||
|
|
smp_mb__after_atomic();
|
||
|
|
|
||
|
|
err = nitrox_crypto_register();
|
||
|
|
if (err)
|
||
|
|
goto crypto_fail;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
crypto_fail:
|
||
|
|
nitrox_debugfs_exit(ndev);
|
||
|
|
atomic_set(&ndev->state, __NDEV_NOT_READY);
|
||
|
|
/* barrier to sync with other cpus */
|
||
|
|
smp_mb__after_atomic();
|
||
|
|
pf_hw_fail:
|
||
|
|
nitrox_pf_sw_cleanup(ndev);
|
||
|
|
ioremap_err:
|
||
|
|
nitrox_remove_from_devlist(ndev);
|
||
|
|
kfree(ndev);
|
||
|
|
pci_set_drvdata(pdev, NULL);
|
||
|
|
ndev_fail:
|
||
|
|
pci_release_mem_regions(pdev);
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* nitrox_remove - Unbind the driver from the device.
|
||
|
|
* @pdev: PCI device information struct
|
||
|
|
*/
|
||
|
|
static void nitrox_remove(struct pci_dev *pdev)
|
||
|
|
{
|
||
|
|
struct nitrox_device *ndev = pci_get_drvdata(pdev);
|
||
|
|
|
||
|
|
if (!ndev)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (!refcount_dec_and_test(&ndev->refcnt)) {
|
||
|
|
dev_err(DEV(ndev), "Device refcnt not zero (%d)\n",
|
||
|
|
refcount_read(&ndev->refcnt));
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_info(DEV(ndev), "Removing Device %x:%x\n",
|
||
|
|
ndev->hw.vendor_id, ndev->hw.device_id);
|
||
|
|
|
||
|
|
atomic_set(&ndev->state, __NDEV_NOT_READY);
|
||
|
|
/* barrier to sync with other cpus */
|
||
|
|
smp_mb__after_atomic();
|
||
|
|
|
||
|
|
nitrox_remove_from_devlist(ndev);
|
||
|
|
|
||
|
|
#ifdef CONFIG_PCI_IOV
|
||
|
|
/* disable SR-IOV */
|
||
|
|
nitrox_sriov_configure(pdev, 0);
|
||
|
|
#endif
|
||
|
|
nitrox_crypto_unregister();
|
||
|
|
nitrox_debugfs_exit(ndev);
|
||
|
|
nitrox_pf_sw_cleanup(ndev);
|
||
|
|
|
||
|
|
iounmap(ndev->bar_addr);
|
||
|
|
kfree(ndev);
|
||
|
|
|
||
|
|
pci_set_drvdata(pdev, NULL);
|
||
|
|
pci_release_mem_regions(pdev);
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void nitrox_shutdown(struct pci_dev *pdev)
|
||
|
|
{
|
||
|
|
pci_set_drvdata(pdev, NULL);
|
||
|
|
pci_release_mem_regions(pdev);
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pci_driver nitrox_driver = {
|
||
|
|
.name = nitrox_driver_name,
|
||
|
|
.id_table = nitrox_pci_tbl,
|
||
|
|
.probe = nitrox_probe,
|
||
|
|
.remove = nitrox_remove,
|
||
|
|
.shutdown = nitrox_shutdown,
|
||
|
|
#ifdef CONFIG_PCI_IOV
|
||
|
|
.sriov_configure = nitrox_sriov_configure,
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
module_pci_driver(nitrox_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Srikanth Jampala <Jampala.Srikanth@cavium.com>");
|
||
|
|
MODULE_DESCRIPTION("Cavium CNN55XX PF Driver" DRIVER_VERSION " ");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_VERSION(DRIVER_VERSION);
|
||
|
|
MODULE_FIRMWARE(SE_FW);
|