365 lines
9.8 KiB
C
365 lines
9.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale QorIQ AHCI SATA platform driver
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*
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* Copyright 2015 Freescale, Inc.
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* Tang Yuantian <Yuantian.Tang@freescale.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/ahci_platform.h>
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#include <linux/device.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/libata.h>
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#include "ahci.h"
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#define DRV_NAME "ahci-qoriq"
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/* port register definition */
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#define PORT_PHY1 0xA8
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#define PORT_PHY2 0xAC
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#define PORT_PHY3 0xB0
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#define PORT_PHY4 0xB4
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#define PORT_PHY5 0xB8
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#define PORT_AXICC 0xBC
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#define PORT_TRANS 0xC8
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/* port register default value */
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe
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#define AHCI_PORT_PHY2_CFG 0x28184d1f
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#define AHCI_PORT_PHY3_CFG 0x0e081509
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#define AHCI_PORT_TRANS_CFG 0x08000029
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#define AHCI_PORT_AXICC_CFG 0x3fffffff
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/* for ls1021a */
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#define LS1021A_PORT_PHY2 0x28183414
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#define LS1021A_PORT_PHY3 0x0e080e06
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#define LS1021A_PORT_PHY4 0x064a080b
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#define LS1021A_PORT_PHY5 0x2aa86470
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#define LS1021A_AXICC_ADDR 0xC0
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#define SATA_ECC_DISABLE 0x00020000
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#define ECC_DIS_ARMV8_CH2 0x80000000
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#define ECC_DIS_LS1088A 0x40000000
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enum ahci_qoriq_type {
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AHCI_LS1021A,
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AHCI_LS1028A,
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AHCI_LS1043A,
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AHCI_LS2080A,
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AHCI_LS1046A,
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AHCI_LS1088A,
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AHCI_LS2088A,
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AHCI_LX2160A,
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};
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struct ahci_qoriq_priv {
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struct ccsr_ahci *reg_base;
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enum ahci_qoriq_type type;
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void __iomem *ecc_addr;
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bool is_dmacoherent;
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};
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static bool ecc_initialized;
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static const struct of_device_id ahci_qoriq_of_match[] = {
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{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
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{ .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
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{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
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{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
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{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
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{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
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{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
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{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
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{},
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};
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MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
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static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
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void __iomem *port_mmio = ahci_port_base(link->ap);
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u32 px_cmd, px_is, px_val;
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struct ata_port *ap = link->ap;
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struct ahci_port_priv *pp = ap->private_data;
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struct ahci_host_priv *hpriv = ap->host->private_data;
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struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
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u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
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struct ata_taskfile tf;
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bool online;
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int rc;
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bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
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DPRINTK("ENTER\n");
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hpriv->stop_engine(ap);
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/*
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* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
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* A-009042: The device detection initialization sequence
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* mistakenly resets some registers.
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*
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* Workaround for this is:
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* The software should read and store PxCMD and PxIS values
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* before issuing the device detection initialization sequence.
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* After the sequence is complete, software should restore the
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* PxCMD and PxIS with the stored values.
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*/
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if (ls1021a_workaround) {
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px_cmd = readl(port_mmio + PORT_CMD);
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px_is = readl(port_mmio + PORT_IRQ_STAT);
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}
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/* clear D2H reception area to properly wait for D2H FIS */
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ata_tf_init(link->device, &tf);
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tf.command = ATA_BUSY;
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ata_tf_to_fis(&tf, 0, 0, d2h_fis);
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rc = sata_link_hardreset(link, timing, deadline, &online,
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ahci_check_ready);
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/* restore the PxCMD and PxIS on ls1021 */
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if (ls1021a_workaround) {
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px_val = readl(port_mmio + PORT_CMD);
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if (px_val != px_cmd)
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writel(px_cmd, port_mmio + PORT_CMD);
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px_val = readl(port_mmio + PORT_IRQ_STAT);
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if (px_val != px_is)
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writel(px_is, port_mmio + PORT_IRQ_STAT);
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}
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hpriv->start_engine(ap);
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if (online)
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*class = ahci_dev_classify(ap);
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DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
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return rc;
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}
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static struct ata_port_operations ahci_qoriq_ops = {
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.inherits = &ahci_ops,
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.hardreset = ahci_qoriq_hardreset,
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};
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static const struct ata_port_info ahci_qoriq_port_info = {
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.flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_qoriq_ops,
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};
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static struct scsi_host_template ahci_qoriq_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
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{
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struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
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void __iomem *reg_base = hpriv->mmio;
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switch (qpriv->type) {
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case AHCI_LS1021A:
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if (!(qpriv->ecc_addr || ecc_initialized))
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return -EINVAL;
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else if (qpriv->ecc_addr && !ecc_initialized)
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writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
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writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
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writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
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writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG,
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reg_base + LS1021A_AXICC_ADDR);
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break;
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case AHCI_LS1043A:
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if (!(qpriv->ecc_addr || ecc_initialized))
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return -EINVAL;
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else if (qpriv->ecc_addr && !ecc_initialized)
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writel(readl(qpriv->ecc_addr) |
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ECC_DIS_ARMV8_CH2,
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qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS2080A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS1046A:
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if (!(qpriv->ecc_addr || ecc_initialized))
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return -EINVAL;
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else if (qpriv->ecc_addr && !ecc_initialized)
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writel(readl(qpriv->ecc_addr) |
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ECC_DIS_ARMV8_CH2,
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qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS1028A:
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case AHCI_LS1088A:
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case AHCI_LX2160A:
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if (!(qpriv->ecc_addr || ecc_initialized))
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return -EINVAL;
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else if (qpriv->ecc_addr && !ecc_initialized)
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writel(readl(qpriv->ecc_addr) |
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ECC_DIS_LS1088A,
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qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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case AHCI_LS2088A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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break;
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}
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ecc_initialized = true;
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return 0;
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}
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static int ahci_qoriq_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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struct ahci_qoriq_priv *qoriq_priv;
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const struct of_device_id *of_id;
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struct resource *res;
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int rc;
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hpriv = ahci_platform_get_resources(pdev, 0);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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of_id = of_match_node(ahci_qoriq_of_match, np);
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if (!of_id)
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return -ENODEV;
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qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
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if (!qoriq_priv)
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return -ENOMEM;
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qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
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if (unlikely(!ecc_initialized)) {
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res = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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"sata-ecc");
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if (res) {
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qoriq_priv->ecc_addr =
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devm_ioremap_resource(dev, res);
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if (IS_ERR(qoriq_priv->ecc_addr))
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return PTR_ERR(qoriq_priv->ecc_addr);
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}
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}
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qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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hpriv->plat_data = qoriq_priv;
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rc = ahci_qoriq_phy_init(hpriv);
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if (rc)
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goto disable_resources;
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
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&ahci_qoriq_sht);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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#ifdef CONFIG_PM_SLEEP
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static int ahci_qoriq_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct ahci_host_priv *hpriv = host->private_data;
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int rc;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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rc = ahci_qoriq_phy_init(hpriv);
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if (rc)
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goto disable_resources;
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rc = ahci_platform_resume_host(dev);
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if (rc)
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goto disable_resources;
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/* We resumed so update PM runtime state */
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pm_runtime_disable(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
disable_resources:
|
||
|
|
ahci_platform_disable_resources(hpriv);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
|
||
|
|
ahci_qoriq_resume);
|
||
|
|
|
||
|
|
static struct platform_driver ahci_qoriq_driver = {
|
||
|
|
.probe = ahci_qoriq_probe,
|
||
|
|
.remove = ata_platform_remove_one,
|
||
|
|
.driver = {
|
||
|
|
.name = DRV_NAME,
|
||
|
|
.of_match_table = ahci_qoriq_of_match,
|
||
|
|
.pm = &ahci_qoriq_pm_ops,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(ahci_qoriq_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
|
||
|
|
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
|
||
|
|
MODULE_LICENSE("GPL");
|