891 lines
23 KiB
C
891 lines
23 KiB
C
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/* Generic MTRR (Memory Type Range Register) driver.
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Copyright (C) 1997-2000 Richard Gooch
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Copyright (c) 2002 Patrick Mochel
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with this library; if not, write to the Free
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Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Richard Gooch may be reached by email at rgooch@atnf.csiro.au
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The postal address is:
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Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
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Source: "Pentium Pro Family Developer's Manual, Volume 3:
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Operating System Writer's Guide" (Intel document number 242692),
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section 11.11.7
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This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
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on 6-7 March 2002.
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Source: Intel Architecture Software Developers Manual, Volume 3:
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System Programming Guide; Section 9.11. (1997 edition - PPro).
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*/
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#define DEBUG
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#include <linux/types.h> /* FIXME: kvm_para.h needs this */
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#include <linux/stop_machine.h>
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#include <linux/kvm_para.h>
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#include <linux/uaccess.h>
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#include <linux/export.h>
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#include <linux/mutex.h>
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#include <linux/init.h>
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#include <linux/sort.h>
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#include <linux/cpu.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <linux/syscore_ops.h>
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#include <linux/rcupdate.h>
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#include <asm/cpufeature.h>
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#include <asm/e820/api.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm/pat.h>
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#include "mtrr.h"
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/* arch_phys_wc_add returns an MTRR register index plus this offset. */
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#define MTRR_TO_PHYS_WC_OFFSET 1000
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u32 num_var_ranges;
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static bool __mtrr_enabled;
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static bool mtrr_enabled(void)
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{
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return __mtrr_enabled;
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}
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unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
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static DEFINE_MUTEX(mtrr_mutex);
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u64 size_or_mask, size_and_mask;
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static bool mtrr_aps_delayed_init;
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static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM] __ro_after_init;
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const struct mtrr_ops *mtrr_if;
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static void set_mtrr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type);
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void __init set_mtrr_ops(const struct mtrr_ops *ops)
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{
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if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
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mtrr_ops[ops->vendor] = ops;
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}
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/* Returns non-zero if we have the write-combining memory type */
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static int have_wrcomb(void)
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{
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struct pci_dev *dev;
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dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
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if (dev != NULL) {
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/*
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* ServerWorks LE chipsets < rev 6 have problems with
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* write-combining. Don't allow it and leave room for other
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* chipsets to be tagged
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*/
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if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
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dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
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dev->revision <= 5) {
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pr_info("Serverworks LE rev < 6 detected. Write-combining disabled.\n");
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pci_dev_put(dev);
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return 0;
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}
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/*
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* Intel 450NX errata # 23. Non ascending cacheline evictions to
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* write combining memory may resulting in data corruption
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*/
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if (dev->vendor == PCI_VENDOR_ID_INTEL &&
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dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
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pr_info("Intel 450NX MMC detected. Write-combining disabled.\n");
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pci_dev_put(dev);
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return 0;
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}
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pci_dev_put(dev);
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}
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return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
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}
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/* This function returns the number of variable MTRRs */
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static void __init set_num_var_ranges(void)
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{
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unsigned long config = 0, dummy;
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if (use_intel())
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rdmsr(MSR_MTRRcap, config, dummy);
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else if (is_cpu(AMD) || is_cpu(HYGON))
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config = 2;
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else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
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config = 8;
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num_var_ranges = config & 0xff;
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}
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static void __init init_table(void)
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{
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int i, max;
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max = num_var_ranges;
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for (i = 0; i < max; i++)
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mtrr_usage_table[i] = 1;
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}
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struct set_mtrr_data {
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unsigned long smp_base;
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unsigned long smp_size;
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unsigned int smp_reg;
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mtrr_type smp_type;
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};
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/**
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* mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
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* by all the CPUs.
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* @info: pointer to mtrr configuration data
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*
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* Returns nothing.
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*/
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static int mtrr_rendezvous_handler(void *info)
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{
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struct set_mtrr_data *data = info;
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/*
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* We use this same function to initialize the mtrrs during boot,
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* resume, runtime cpu online and on an explicit request to set a
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* specific MTRR.
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*
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* During boot or suspend, the state of the boot cpu's mtrrs has been
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* saved, and we want to replicate that across all the cpus that come
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* online (either at the end of boot or resume or during a runtime cpu
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* online). If we're doing that, @reg is set to something special and on
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* all the cpu's we do mtrr_if->set_all() (On the logical cpu that
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* started the boot/resume sequence, this might be a duplicate
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* set_all()).
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*/
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if (data->smp_reg != ~0U) {
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mtrr_if->set(data->smp_reg, data->smp_base,
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data->smp_size, data->smp_type);
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} else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
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mtrr_if->set_all();
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}
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return 0;
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}
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static inline int types_compatible(mtrr_type type1, mtrr_type type2)
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{
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return type1 == MTRR_TYPE_UNCACHABLE ||
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type2 == MTRR_TYPE_UNCACHABLE ||
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(type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
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(type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
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}
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/**
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* set_mtrr - update mtrrs on all processors
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* @reg: mtrr in question
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* @base: mtrr base
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* @size: mtrr size
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* @type: mtrr type
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*
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* This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
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*
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* 1. Queue work to do the following on all processors:
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* 2. Disable Interrupts
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* 3. Wait for all procs to do so
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* 4. Enter no-fill cache mode
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* 5. Flush caches
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* 6. Clear PGE bit
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* 7. Flush all TLBs
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* 8. Disable all range registers
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* 9. Update the MTRRs
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* 10. Enable all range registers
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* 11. Flush all TLBs and caches again
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* 12. Enter normal cache mode and reenable caching
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* 13. Set PGE
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* 14. Wait for buddies to catch up
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* 15. Enable interrupts.
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*
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* What does that mean for us? Well, stop_machine() will ensure that
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* the rendezvous handler is started on each CPU. And in lockstep they
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* do the state transition of disabling interrupts, updating MTRR's
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* (the CPU vendors may each do it differently, so we call mtrr_if->set()
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* callback and let them take care of it.) and enabling interrupts.
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*
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* Note that the mechanism is the same for UP systems, too; all the SMP stuff
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* becomes nops.
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*/
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static void
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set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
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{
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struct set_mtrr_data data = { .smp_reg = reg,
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.smp_base = base,
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.smp_size = size,
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.smp_type = type
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};
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stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask);
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}
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static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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{
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struct set_mtrr_data data = { .smp_reg = reg,
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.smp_base = base,
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.smp_size = size,
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.smp_type = type
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};
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stop_machine_cpuslocked(mtrr_rendezvous_handler, &data, cpu_online_mask);
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}
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static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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{
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struct set_mtrr_data data = { .smp_reg = reg,
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.smp_base = base,
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.smp_size = size,
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.smp_type = type
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};
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stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data,
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cpu_callout_mask);
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}
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/**
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* mtrr_add_page - Add a memory type region
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* @base: Physical base address of region in pages (in units of 4 kB!)
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* @size: Physical size of region in pages (4 kB)
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* @type: Type of MTRR desired
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* @increment: If this is true do usage counting on the region
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*
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* Memory type region registers control the caching on newer Intel and
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* non Intel processors. This function allows drivers to request an
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* MTRR is added. The details and hardware specifics of each processor's
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* implementation are hidden from the caller, but nevertheless the
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* caller should expect to need to provide a power of two size on an
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* equivalent power of two boundary.
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*
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* If the region cannot be added either because all regions are in use
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* or the CPU cannot support it a negative value is returned. On success
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* the register number for this entry is returned, but should be treated
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* as a cookie only.
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*
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* On a multiprocessor machine the changes are made to all processors.
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* This is required on x86 by the Intel processors.
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*
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* The available types are
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*
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* %MTRR_TYPE_UNCACHABLE - No caching
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*
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* %MTRR_TYPE_WRBACK - Write data back in bursts whenever
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*
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* %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
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*
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* %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
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*
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* BUGS: Needs a quiet flag for the cases where drivers do not mind
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* failures and do not wish system log messages to be sent.
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*/
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int mtrr_add_page(unsigned long base, unsigned long size,
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unsigned int type, bool increment)
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{
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unsigned long lbase, lsize;
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int i, replace, error;
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mtrr_type ltype;
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if (!mtrr_enabled())
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return -ENXIO;
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error = mtrr_if->validate_add_page(base, size, type);
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if (error)
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return error;
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if (type >= MTRR_NUM_TYPES) {
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pr_warn("type: %u invalid\n", type);
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return -EINVAL;
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}
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/* If the type is WC, check that this processor supports it */
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if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
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pr_warn("your processor doesn't support write-combining\n");
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return -ENOSYS;
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}
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if (!size) {
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pr_warn("zero sized request\n");
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return -EINVAL;
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}
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if ((base | (base + size - 1)) >>
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(boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
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pr_warn("base or size exceeds the MTRR width\n");
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return -EINVAL;
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}
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error = -EINVAL;
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replace = -1;
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/* No CPU hotplug when we change MTRR entries */
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get_online_cpus();
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/* Search for existing MTRR */
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mutex_lock(&mtrr_mutex);
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for (i = 0; i < num_var_ranges; ++i) {
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (!lsize || base > lbase + lsize - 1 ||
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base + size - 1 < lbase)
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continue;
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/*
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* At this point we know there is some kind of
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* overlap/enclosure
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*/
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if (base < lbase || base + size - 1 > lbase + lsize - 1) {
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if (base <= lbase &&
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base + size - 1 >= lbase + lsize - 1) {
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/* New region encloses an existing region */
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if (type == ltype) {
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replace = replace == -1 ? i : -2;
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continue;
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} else if (types_compatible(type, ltype))
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continue;
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}
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|
|
pr_warn("0x%lx000,0x%lx000 overlaps existing 0x%lx000,0x%lx000\n", base, size, lbase,
|
||
|
|
lsize);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
/* New region is enclosed by an existing region */
|
||
|
|
if (ltype != type) {
|
||
|
|
if (types_compatible(type, ltype))
|
||
|
|
continue;
|
||
|
|
pr_warn("type mismatch for %lx000,%lx000 old: %s new: %s\n",
|
||
|
|
base, size, mtrr_attrib_to_str(ltype),
|
||
|
|
mtrr_attrib_to_str(type));
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
if (increment)
|
||
|
|
++mtrr_usage_table[i];
|
||
|
|
error = i;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
/* Search for an empty MTRR */
|
||
|
|
i = mtrr_if->get_free_region(base, size, replace);
|
||
|
|
if (i >= 0) {
|
||
|
|
set_mtrr_cpuslocked(i, base, size, type);
|
||
|
|
if (likely(replace < 0)) {
|
||
|
|
mtrr_usage_table[i] = 1;
|
||
|
|
} else {
|
||
|
|
mtrr_usage_table[i] = mtrr_usage_table[replace];
|
||
|
|
if (increment)
|
||
|
|
mtrr_usage_table[i]++;
|
||
|
|
if (unlikely(replace != i)) {
|
||
|
|
set_mtrr_cpuslocked(replace, 0, 0, 0);
|
||
|
|
mtrr_usage_table[replace] = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
pr_info("no more MTRRs available\n");
|
||
|
|
}
|
||
|
|
error = i;
|
||
|
|
out:
|
||
|
|
mutex_unlock(&mtrr_mutex);
|
||
|
|
put_online_cpus();
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mtrr_check(unsigned long base, unsigned long size)
|
||
|
|
{
|
||
|
|
if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
|
||
|
|
pr_warn("size and base must be multiples of 4 kiB\n");
|
||
|
|
pr_debug("size: 0x%lx base: 0x%lx\n", size, base);
|
||
|
|
dump_stack();
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* mtrr_add - Add a memory type region
|
||
|
|
* @base: Physical base address of region
|
||
|
|
* @size: Physical size of region
|
||
|
|
* @type: Type of MTRR desired
|
||
|
|
* @increment: If this is true do usage counting on the region
|
||
|
|
*
|
||
|
|
* Memory type region registers control the caching on newer Intel and
|
||
|
|
* non Intel processors. This function allows drivers to request an
|
||
|
|
* MTRR is added. The details and hardware specifics of each processor's
|
||
|
|
* implementation are hidden from the caller, but nevertheless the
|
||
|
|
* caller should expect to need to provide a power of two size on an
|
||
|
|
* equivalent power of two boundary.
|
||
|
|
*
|
||
|
|
* If the region cannot be added either because all regions are in use
|
||
|
|
* or the CPU cannot support it a negative value is returned. On success
|
||
|
|
* the register number for this entry is returned, but should be treated
|
||
|
|
* as a cookie only.
|
||
|
|
*
|
||
|
|
* On a multiprocessor machine the changes are made to all processors.
|
||
|
|
* This is required on x86 by the Intel processors.
|
||
|
|
*
|
||
|
|
* The available types are
|
||
|
|
*
|
||
|
|
* %MTRR_TYPE_UNCACHABLE - No caching
|
||
|
|
*
|
||
|
|
* %MTRR_TYPE_WRBACK - Write data back in bursts whenever
|
||
|
|
*
|
||
|
|
* %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
|
||
|
|
*
|
||
|
|
* %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
|
||
|
|
*
|
||
|
|
* BUGS: Needs a quiet flag for the cases where drivers do not mind
|
||
|
|
* failures and do not wish system log messages to be sent.
|
||
|
|
*/
|
||
|
|
int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
|
||
|
|
bool increment)
|
||
|
|
{
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return -ENODEV;
|
||
|
|
if (mtrr_check(base, size))
|
||
|
|
return -EINVAL;
|
||
|
|
return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
|
||
|
|
increment);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* mtrr_del_page - delete a memory type region
|
||
|
|
* @reg: Register returned by mtrr_add
|
||
|
|
* @base: Physical base address
|
||
|
|
* @size: Size of region
|
||
|
|
*
|
||
|
|
* If register is supplied then base and size are ignored. This is
|
||
|
|
* how drivers should call it.
|
||
|
|
*
|
||
|
|
* Releases an MTRR region. If the usage count drops to zero the
|
||
|
|
* register is freed and the region returns to default state.
|
||
|
|
* On success the register is returned, on failure a negative error
|
||
|
|
* code.
|
||
|
|
*/
|
||
|
|
int mtrr_del_page(int reg, unsigned long base, unsigned long size)
|
||
|
|
{
|
||
|
|
int i, max;
|
||
|
|
mtrr_type ltype;
|
||
|
|
unsigned long lbase, lsize;
|
||
|
|
int error = -EINVAL;
|
||
|
|
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
max = num_var_ranges;
|
||
|
|
/* No CPU hotplug when we change MTRR entries */
|
||
|
|
get_online_cpus();
|
||
|
|
mutex_lock(&mtrr_mutex);
|
||
|
|
if (reg < 0) {
|
||
|
|
/* Search for existing MTRR */
|
||
|
|
for (i = 0; i < max; ++i) {
|
||
|
|
mtrr_if->get(i, &lbase, &lsize, <ype);
|
||
|
|
if (lbase == base && lsize == size) {
|
||
|
|
reg = i;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (reg < 0) {
|
||
|
|
pr_debug("no MTRR for %lx000,%lx000 found\n",
|
||
|
|
base, size);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (reg >= max) {
|
||
|
|
pr_warn("register: %d too big\n", reg);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
mtrr_if->get(reg, &lbase, &lsize, <ype);
|
||
|
|
if (lsize < 1) {
|
||
|
|
pr_warn("MTRR %d not used\n", reg);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
if (mtrr_usage_table[reg] < 1) {
|
||
|
|
pr_warn("reg: %d has count=0\n", reg);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
if (--mtrr_usage_table[reg] < 1)
|
||
|
|
set_mtrr_cpuslocked(reg, 0, 0, 0);
|
||
|
|
error = reg;
|
||
|
|
out:
|
||
|
|
mutex_unlock(&mtrr_mutex);
|
||
|
|
put_online_cpus();
|
||
|
|
return error;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* mtrr_del - delete a memory type region
|
||
|
|
* @reg: Register returned by mtrr_add
|
||
|
|
* @base: Physical base address
|
||
|
|
* @size: Size of region
|
||
|
|
*
|
||
|
|
* If register is supplied then base and size are ignored. This is
|
||
|
|
* how drivers should call it.
|
||
|
|
*
|
||
|
|
* Releases an MTRR region. If the usage count drops to zero the
|
||
|
|
* register is freed and the region returns to default state.
|
||
|
|
* On success the register is returned, on failure a negative error
|
||
|
|
* code.
|
||
|
|
*/
|
||
|
|
int mtrr_del(int reg, unsigned long base, unsigned long size)
|
||
|
|
{
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return -ENODEV;
|
||
|
|
if (mtrr_check(base, size))
|
||
|
|
return -EINVAL;
|
||
|
|
return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable
|
||
|
|
* @base: Physical base address
|
||
|
|
* @size: Size of region
|
||
|
|
*
|
||
|
|
* If PAT is available, this does nothing. If PAT is unavailable, it
|
||
|
|
* attempts to add a WC MTRR covering size bytes starting at base and
|
||
|
|
* logs an error if this fails.
|
||
|
|
*
|
||
|
|
* The called should provide a power of two size on an equivalent
|
||
|
|
* power of two boundary.
|
||
|
|
*
|
||
|
|
* Drivers must store the return value to pass to mtrr_del_wc_if_needed,
|
||
|
|
* but drivers should not try to interpret that return value.
|
||
|
|
*/
|
||
|
|
int arch_phys_wc_add(unsigned long base, unsigned long size)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (pat_enabled() || !mtrr_enabled())
|
||
|
|
return 0; /* Success! (We don't need to do anything.) */
|
||
|
|
|
||
|
|
ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true);
|
||
|
|
if (ret < 0) {
|
||
|
|
pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.",
|
||
|
|
(void *)base, (void *)(base + size - 1));
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
return ret + MTRR_TO_PHYS_WC_OFFSET;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(arch_phys_wc_add);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* arch_phys_wc_del - undoes arch_phys_wc_add
|
||
|
|
* @handle: Return value from arch_phys_wc_add
|
||
|
|
*
|
||
|
|
* This cleans up after mtrr_add_wc_if_needed.
|
||
|
|
*
|
||
|
|
* The API guarantees that mtrr_del_wc_if_needed(error code) and
|
||
|
|
* mtrr_del_wc_if_needed(0) do nothing.
|
||
|
|
*/
|
||
|
|
void arch_phys_wc_del(int handle)
|
||
|
|
{
|
||
|
|
if (handle >= 1) {
|
||
|
|
WARN_ON(handle < MTRR_TO_PHYS_WC_OFFSET);
|
||
|
|
mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(arch_phys_wc_del);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* arch_phys_wc_index - translates arch_phys_wc_add's return value
|
||
|
|
* @handle: Return value from arch_phys_wc_add
|
||
|
|
*
|
||
|
|
* This will turn the return value from arch_phys_wc_add into an mtrr
|
||
|
|
* index suitable for debugging.
|
||
|
|
*
|
||
|
|
* Note: There is no legitimate use for this function, except possibly
|
||
|
|
* in printk line. Alas there is an illegitimate use in some ancient
|
||
|
|
* drm ioctls.
|
||
|
|
*/
|
||
|
|
int arch_phys_wc_index(int handle)
|
||
|
|
{
|
||
|
|
if (handle < MTRR_TO_PHYS_WC_OFFSET)
|
||
|
|
return -1;
|
||
|
|
else
|
||
|
|
return handle - MTRR_TO_PHYS_WC_OFFSET;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(arch_phys_wc_index);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* HACK ALERT!
|
||
|
|
* These should be called implicitly, but we can't yet until all the initcall
|
||
|
|
* stuff is done...
|
||
|
|
*/
|
||
|
|
static void __init init_ifs(void)
|
||
|
|
{
|
||
|
|
#ifndef CONFIG_X86_64
|
||
|
|
amd_init_mtrr();
|
||
|
|
cyrix_init_mtrr();
|
||
|
|
centaur_init_mtrr();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/* The suspend/resume methods are only for CPU without MTRR. CPU using generic
|
||
|
|
* MTRR driver doesn't require this
|
||
|
|
*/
|
||
|
|
struct mtrr_value {
|
||
|
|
mtrr_type ltype;
|
||
|
|
unsigned long lbase;
|
||
|
|
unsigned long lsize;
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
|
||
|
|
|
||
|
|
static int mtrr_save(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < num_var_ranges; i++) {
|
||
|
|
mtrr_if->get(i, &mtrr_value[i].lbase,
|
||
|
|
&mtrr_value[i].lsize,
|
||
|
|
&mtrr_value[i].ltype);
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mtrr_restore(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < num_var_ranges; i++) {
|
||
|
|
if (mtrr_value[i].lsize) {
|
||
|
|
set_mtrr(i, mtrr_value[i].lbase,
|
||
|
|
mtrr_value[i].lsize,
|
||
|
|
mtrr_value[i].ltype);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
static struct syscore_ops mtrr_syscore_ops = {
|
||
|
|
.suspend = mtrr_save,
|
||
|
|
.resume = mtrr_restore,
|
||
|
|
};
|
||
|
|
|
||
|
|
int __initdata changed_by_mtrr_cleanup;
|
||
|
|
|
||
|
|
#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
|
||
|
|
/**
|
||
|
|
* mtrr_bp_init - initialize mtrrs on the boot CPU
|
||
|
|
*
|
||
|
|
* This needs to be called early; before any of the other CPUs are
|
||
|
|
* initialized (i.e. before smp_init()).
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void __init mtrr_bp_init(void)
|
||
|
|
{
|
||
|
|
u32 phys_addr;
|
||
|
|
|
||
|
|
init_ifs();
|
||
|
|
|
||
|
|
phys_addr = 32;
|
||
|
|
|
||
|
|
if (boot_cpu_has(X86_FEATURE_MTRR)) {
|
||
|
|
mtrr_if = &generic_mtrr_ops;
|
||
|
|
size_or_mask = SIZE_OR_MASK_BITS(36);
|
||
|
|
size_and_mask = 0x00f00000;
|
||
|
|
phys_addr = 36;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This is an AMD specific MSR, but we assume(hope?) that
|
||
|
|
* Intel will implement it too when they extend the address
|
||
|
|
* bus of the Xeon.
|
||
|
|
*/
|
||
|
|
if (cpuid_eax(0x80000000) >= 0x80000008) {
|
||
|
|
phys_addr = cpuid_eax(0x80000008) & 0xff;
|
||
|
|
/* CPUID workaround for Intel 0F33/0F34 CPU */
|
||
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
|
||
|
|
boot_cpu_data.x86 == 0xF &&
|
||
|
|
boot_cpu_data.x86_model == 0x3 &&
|
||
|
|
(boot_cpu_data.x86_stepping == 0x3 ||
|
||
|
|
boot_cpu_data.x86_stepping == 0x4))
|
||
|
|
phys_addr = 36;
|
||
|
|
|
||
|
|
size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
|
||
|
|
size_and_mask = ~size_or_mask & 0xfffff00000ULL;
|
||
|
|
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
|
||
|
|
boot_cpu_data.x86 == 6) {
|
||
|
|
/*
|
||
|
|
* VIA C* family have Intel style MTRRs,
|
||
|
|
* but don't support PAE
|
||
|
|
*/
|
||
|
|
size_or_mask = SIZE_OR_MASK_BITS(32);
|
||
|
|
size_and_mask = 0;
|
||
|
|
phys_addr = 32;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
switch (boot_cpu_data.x86_vendor) {
|
||
|
|
case X86_VENDOR_AMD:
|
||
|
|
if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) {
|
||
|
|
/* Pre-Athlon (K6) AMD CPU MTRRs */
|
||
|
|
mtrr_if = mtrr_ops[X86_VENDOR_AMD];
|
||
|
|
size_or_mask = SIZE_OR_MASK_BITS(32);
|
||
|
|
size_and_mask = 0;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case X86_VENDOR_CENTAUR:
|
||
|
|
if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) {
|
||
|
|
mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
|
||
|
|
size_or_mask = SIZE_OR_MASK_BITS(32);
|
||
|
|
size_and_mask = 0;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case X86_VENDOR_CYRIX:
|
||
|
|
if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) {
|
||
|
|
mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
|
||
|
|
size_or_mask = SIZE_OR_MASK_BITS(32);
|
||
|
|
size_and_mask = 0;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (mtrr_if) {
|
||
|
|
__mtrr_enabled = true;
|
||
|
|
set_num_var_ranges();
|
||
|
|
init_table();
|
||
|
|
if (use_intel()) {
|
||
|
|
/* BIOS may override */
|
||
|
|
__mtrr_enabled = get_mtrr_state();
|
||
|
|
|
||
|
|
if (mtrr_enabled())
|
||
|
|
mtrr_bp_pat_init();
|
||
|
|
|
||
|
|
if (mtrr_cleanup(phys_addr)) {
|
||
|
|
changed_by_mtrr_cleanup = 1;
|
||
|
|
mtrr_if->set_all();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!mtrr_enabled()) {
|
||
|
|
pr_info("Disabled\n");
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PAT initialization relies on MTRR's rendezvous handler.
|
||
|
|
* Skip PAT init until the handler can initialize both
|
||
|
|
* features independently.
|
||
|
|
*/
|
||
|
|
pat_disable("MTRRs disabled, skipping PAT initialization too.");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void mtrr_ap_init(void)
|
||
|
|
{
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (!use_intel() || mtrr_aps_delayed_init)
|
||
|
|
return;
|
||
|
|
|
||
|
|
rcu_cpu_starting(smp_processor_id());
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Ideally we should hold mtrr_mutex here to avoid mtrr entries
|
||
|
|
* changed, but this routine will be called in cpu boot time,
|
||
|
|
* holding the lock breaks it.
|
||
|
|
*
|
||
|
|
* This routine is called in two cases:
|
||
|
|
*
|
||
|
|
* 1. very earily time of software resume, when there absolutely
|
||
|
|
* isn't mtrr entry changes;
|
||
|
|
*
|
||
|
|
* 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
|
||
|
|
* lock to prevent mtrr entry changes
|
||
|
|
*/
|
||
|
|
set_mtrr_from_inactive_cpu(~0U, 0, 0, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Save current fixed-range MTRR state of the first cpu in cpu_online_mask.
|
||
|
|
*/
|
||
|
|
void mtrr_save_state(void)
|
||
|
|
{
|
||
|
|
int first_cpu;
|
||
|
|
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return;
|
||
|
|
|
||
|
|
first_cpu = cpumask_first(cpu_online_mask);
|
||
|
|
smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
void set_mtrr_aps_delayed_init(void)
|
||
|
|
{
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return;
|
||
|
|
if (!use_intel())
|
||
|
|
return;
|
||
|
|
|
||
|
|
mtrr_aps_delayed_init = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Delayed MTRR initialization for all AP's
|
||
|
|
*/
|
||
|
|
void mtrr_aps_init(void)
|
||
|
|
{
|
||
|
|
if (!use_intel() || !mtrr_enabled())
|
||
|
|
return;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check if someone has requested the delay of AP MTRR initialization,
|
||
|
|
* by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
|
||
|
|
* then we are done.
|
||
|
|
*/
|
||
|
|
if (!mtrr_aps_delayed_init)
|
||
|
|
return;
|
||
|
|
|
||
|
|
set_mtrr(~0U, 0, 0, 0);
|
||
|
|
mtrr_aps_delayed_init = false;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mtrr_bp_restore(void)
|
||
|
|
{
|
||
|
|
if (!use_intel() || !mtrr_enabled())
|
||
|
|
return;
|
||
|
|
|
||
|
|
mtrr_if->set_all();
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init mtrr_init_finialize(void)
|
||
|
|
{
|
||
|
|
if (!mtrr_enabled())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
if (use_intel()) {
|
||
|
|
if (!changed_by_mtrr_cleanup)
|
||
|
|
mtrr_state_warn();
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The CPU has no MTRR and seems to not support SMP. They have
|
||
|
|
* specific drivers, we use a tricky method to support
|
||
|
|
* suspend/resume for them.
|
||
|
|
*
|
||
|
|
* TBD: is there any system with such CPU which supports
|
||
|
|
* suspend/resume? If no, we should remove the code.
|
||
|
|
*/
|
||
|
|
register_syscore_ops(&mtrr_syscore_ops);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
subsys_initcall(mtrr_init_finialize);
|