422 lines
9.5 KiB
C
422 lines
9.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/highmem.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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/* #define DEBUG_MMU */
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/* #define DEBUG_MMU_PTE */
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/* #define DEBUG_MMU_PTE_IP 0xfff14c40 */
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#ifdef DEBUG_MMU
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#define dprintk(X...) printk(KERN_INFO X)
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#else
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#define dprintk(X...) do { } while(0)
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#endif
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#ifdef DEBUG_MMU_PTE
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#define dprintk_pte(X...) printk(KERN_INFO X)
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#else
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#define dprintk_pte(X...) do { } while(0)
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#endif
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#define PTEG_FLAG_ACCESSED 0x00000100
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#define PTEG_FLAG_DIRTY 0x00000080
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#ifndef SID_SHIFT
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#define SID_SHIFT 28
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#endif
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static inline bool check_debug_ip(struct kvm_vcpu *vcpu)
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{
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#ifdef DEBUG_MMU_PTE_IP
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return vcpu->arch.regs.nip == DEBUG_MMU_PTE_IP;
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#else
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return true;
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#endif
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}
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static inline u32 sr_vsid(u32 sr_raw)
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{
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return sr_raw & 0x0fffffff;
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}
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static inline bool sr_valid(u32 sr_raw)
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{
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return (sr_raw & 0x80000000) ? false : true;
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}
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static inline bool sr_ks(u32 sr_raw)
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{
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return (sr_raw & 0x40000000) ? true: false;
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}
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static inline bool sr_kp(u32 sr_raw)
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{
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return (sr_raw & 0x20000000) ? true: false;
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}
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static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr,
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struct kvmppc_pte *pte, bool data,
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bool iswrite);
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static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid,
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u64 *vsid);
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static u32 find_sr(struct kvm_vcpu *vcpu, gva_t eaddr)
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{
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return kvmppc_get_sr(vcpu, (eaddr >> 28) & 0xf);
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}
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static u64 kvmppc_mmu_book3s_32_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
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bool data)
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{
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u64 vsid;
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struct kvmppc_pte pte;
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if (!kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, &pte, data, false))
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return pte.vpage;
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kvmppc_mmu_book3s_32_esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid);
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return (((u64)eaddr >> 12) & 0xffff) | (vsid << 16);
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}
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static void kvmppc_mmu_book3s_32_reset_msr(struct kvm_vcpu *vcpu)
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{
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kvmppc_set_msr(vcpu, 0);
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}
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static hva_t kvmppc_mmu_book3s_32_get_pteg(struct kvm_vcpu *vcpu,
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u32 sre, gva_t eaddr,
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bool primary)
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{
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struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
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u32 page, hash, pteg, htabmask;
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hva_t r;
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page = (eaddr & 0x0FFFFFFF) >> 12;
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htabmask = ((vcpu_book3s->sdr1 & 0x1FF) << 16) | 0xFFC0;
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hash = ((sr_vsid(sre) ^ page) << 6);
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if (!primary)
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hash = ~hash;
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hash &= htabmask;
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pteg = (vcpu_book3s->sdr1 & 0xffff0000) | hash;
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dprintk("MMU: pc=0x%lx eaddr=0x%lx sdr1=0x%llx pteg=0x%x vsid=0x%x\n",
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kvmppc_get_pc(vcpu), eaddr, vcpu_book3s->sdr1, pteg,
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sr_vsid(sre));
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r = gfn_to_hva(vcpu->kvm, pteg >> PAGE_SHIFT);
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if (kvm_is_error_hva(r))
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return r;
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return r | (pteg & ~PAGE_MASK);
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}
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static u32 kvmppc_mmu_book3s_32_get_ptem(u32 sre, gva_t eaddr, bool primary)
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{
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return ((eaddr & 0x0fffffff) >> 22) | (sr_vsid(sre) << 7) |
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(primary ? 0 : 0x40) | 0x80000000;
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}
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static int kvmppc_mmu_book3s_32_xlate_bat(struct kvm_vcpu *vcpu, gva_t eaddr,
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struct kvmppc_pte *pte, bool data,
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bool iswrite)
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{
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struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
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struct kvmppc_bat *bat;
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int i;
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for (i = 0; i < 8; i++) {
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if (data)
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bat = &vcpu_book3s->dbat[i];
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else
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bat = &vcpu_book3s->ibat[i];
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if (kvmppc_get_msr(vcpu) & MSR_PR) {
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if (!bat->vp)
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continue;
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} else {
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if (!bat->vs)
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continue;
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}
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if (check_debug_ip(vcpu))
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{
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dprintk_pte("%cBAT %02d: 0x%lx - 0x%x (0x%x)\n",
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data ? 'd' : 'i', i, eaddr, bat->bepi,
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bat->bepi_mask);
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}
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if ((eaddr & bat->bepi_mask) == bat->bepi) {
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u64 vsid;
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kvmppc_mmu_book3s_32_esid_to_vsid(vcpu,
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eaddr >> SID_SHIFT, &vsid);
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vsid <<= 16;
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pte->vpage = (((u64)eaddr >> 12) & 0xffff) | vsid;
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pte->raddr = bat->brpn | (eaddr & ~bat->bepi_mask);
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pte->may_read = bat->pp;
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pte->may_write = bat->pp > 1;
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pte->may_execute = true;
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if (!pte->may_read) {
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printk(KERN_INFO "BAT is not readable!\n");
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continue;
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}
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if (iswrite && !pte->may_write) {
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dprintk_pte("BAT is read-only!\n");
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continue;
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}
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return 0;
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}
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}
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return -ENOENT;
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}
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static int kvmppc_mmu_book3s_32_xlate_pte(struct kvm_vcpu *vcpu, gva_t eaddr,
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struct kvmppc_pte *pte, bool data,
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bool iswrite, bool primary)
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{
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u32 sre;
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hva_t ptegp;
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u32 pteg[16];
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u32 pte0, pte1;
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u32 ptem = 0;
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int i;
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int found = 0;
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sre = find_sr(vcpu, eaddr);
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dprintk_pte("SR 0x%lx: vsid=0x%x, raw=0x%x\n", eaddr >> 28,
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sr_vsid(sre), sre);
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pte->vpage = kvmppc_mmu_book3s_32_ea_to_vp(vcpu, eaddr, data);
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ptegp = kvmppc_mmu_book3s_32_get_pteg(vcpu, sre, eaddr, primary);
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if (kvm_is_error_hva(ptegp)) {
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printk(KERN_INFO "KVM: Invalid PTEG!\n");
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goto no_page_found;
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}
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ptem = kvmppc_mmu_book3s_32_get_ptem(sre, eaddr, primary);
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if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) {
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printk_ratelimited(KERN_ERR
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"KVM: Can't copy data from 0x%lx!\n", ptegp);
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goto no_page_found;
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}
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for (i=0; i<16; i+=2) {
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pte0 = be32_to_cpu(pteg[i]);
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pte1 = be32_to_cpu(pteg[i + 1]);
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if (ptem == pte0) {
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u8 pp;
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pte->raddr = (pte1 & ~(0xFFFULL)) | (eaddr & 0xFFF);
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pp = pte1 & 3;
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if ((sr_kp(sre) && (kvmppc_get_msr(vcpu) & MSR_PR)) ||
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(sr_ks(sre) && !(kvmppc_get_msr(vcpu) & MSR_PR)))
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pp |= 4;
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pte->may_write = false;
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pte->may_read = false;
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pte->may_execute = true;
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switch (pp) {
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case 0:
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case 1:
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case 2:
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case 6:
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pte->may_write = true;
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/* fall through */
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case 3:
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case 5:
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case 7:
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pte->may_read = true;
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break;
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}
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dprintk_pte("MMU: Found PTE -> %x %x - %x\n",
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pte0, pte1, pp);
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found = 1;
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break;
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}
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}
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/* Update PTE C and A bits, so the guest's swapper knows we used the
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page */
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if (found) {
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u32 pte_r = pte1;
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char __user *addr = (char __user *) (ptegp + (i+1) * sizeof(u32));
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/*
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* Use single-byte writes to update the HPTE, to
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* conform to what real hardware does.
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*/
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if (pte->may_read && !(pte_r & PTEG_FLAG_ACCESSED)) {
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pte_r |= PTEG_FLAG_ACCESSED;
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put_user(pte_r >> 8, addr + 2);
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}
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if (iswrite && pte->may_write && !(pte_r & PTEG_FLAG_DIRTY)) {
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pte_r |= PTEG_FLAG_DIRTY;
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put_user(pte_r, addr + 3);
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}
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if (!pte->may_read || (iswrite && !pte->may_write))
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return -EPERM;
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return 0;
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}
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no_page_found:
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if (check_debug_ip(vcpu)) {
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dprintk_pte("KVM MMU: No PTE found (sdr1=0x%llx ptegp=0x%lx)\n",
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to_book3s(vcpu)->sdr1, ptegp);
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for (i=0; i<16; i+=2) {
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dprintk_pte(" %02d: 0x%x - 0x%x (0x%x)\n",
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i, be32_to_cpu(pteg[i]),
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be32_to_cpu(pteg[i+1]), ptem);
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}
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}
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return -ENOENT;
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}
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static int kvmppc_mmu_book3s_32_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
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struct kvmppc_pte *pte, bool data,
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bool iswrite)
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{
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int r;
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ulong mp_ea = vcpu->arch.magic_page_ea;
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pte->eaddr = eaddr;
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pte->page_size = MMU_PAGE_4K;
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/* Magic page override */
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if (unlikely(mp_ea) &&
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unlikely((eaddr & ~0xfffULL) == (mp_ea & ~0xfffULL)) &&
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!(kvmppc_get_msr(vcpu) & MSR_PR)) {
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pte->vpage = kvmppc_mmu_book3s_32_ea_to_vp(vcpu, eaddr, data);
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pte->raddr = vcpu->arch.magic_page_pa | (pte->raddr & 0xfff);
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pte->raddr &= KVM_PAM;
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pte->may_execute = true;
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pte->may_read = true;
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pte->may_write = true;
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return 0;
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}
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r = kvmppc_mmu_book3s_32_xlate_bat(vcpu, eaddr, pte, data, iswrite);
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if (r < 0)
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r = kvmppc_mmu_book3s_32_xlate_pte(vcpu, eaddr, pte,
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data, iswrite, true);
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if (r == -ENOENT)
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r = kvmppc_mmu_book3s_32_xlate_pte(vcpu, eaddr, pte,
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data, iswrite, false);
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return r;
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}
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static u32 kvmppc_mmu_book3s_32_mfsrin(struct kvm_vcpu *vcpu, u32 srnum)
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{
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return kvmppc_get_sr(vcpu, srnum);
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}
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static void kvmppc_mmu_book3s_32_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
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ulong value)
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{
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kvmppc_set_sr(vcpu, srnum, value);
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kvmppc_mmu_map_segment(vcpu, srnum << SID_SHIFT);
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}
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static void kvmppc_mmu_book3s_32_tlbie(struct kvm_vcpu *vcpu, ulong ea, bool large)
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{
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int i;
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struct kvm_vcpu *v;
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/* flush this VA on all cpus */
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kvm_for_each_vcpu(i, v, vcpu->kvm)
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kvmppc_mmu_pte_flush(v, ea, 0x0FFFF000);
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}
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static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid,
|
||
|
|
u64 *vsid)
|
||
|
|
{
|
||
|
|
ulong ea = esid << SID_SHIFT;
|
||
|
|
u32 sr;
|
||
|
|
u64 gvsid = esid;
|
||
|
|
u64 msr = kvmppc_get_msr(vcpu);
|
||
|
|
|
||
|
|
if (msr & (MSR_DR|MSR_IR)) {
|
||
|
|
sr = find_sr(vcpu, ea);
|
||
|
|
if (sr_valid(sr))
|
||
|
|
gvsid = sr_vsid(sr);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* In case we only have one of MSR_IR or MSR_DR set, let's put
|
||
|
|
that in the real-mode context (and hope RM doesn't access
|
||
|
|
high memory) */
|
||
|
|
switch (msr & (MSR_DR|MSR_IR)) {
|
||
|
|
case 0:
|
||
|
|
*vsid = VSID_REAL | esid;
|
||
|
|
break;
|
||
|
|
case MSR_IR:
|
||
|
|
*vsid = VSID_REAL_IR | gvsid;
|
||
|
|
break;
|
||
|
|
case MSR_DR:
|
||
|
|
*vsid = VSID_REAL_DR | gvsid;
|
||
|
|
break;
|
||
|
|
case MSR_DR|MSR_IR:
|
||
|
|
if (sr_valid(sr))
|
||
|
|
*vsid = sr_vsid(sr);
|
||
|
|
else
|
||
|
|
*vsid = VSID_BAT | gvsid;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
BUG();
|
||
|
|
}
|
||
|
|
|
||
|
|
if (msr & MSR_PR)
|
||
|
|
*vsid |= VSID_PR;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool kvmppc_mmu_book3s_32_is_dcbz32(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
struct kvmppc_mmu *mmu = &vcpu->arch.mmu;
|
||
|
|
|
||
|
|
mmu->mtsrin = kvmppc_mmu_book3s_32_mtsrin;
|
||
|
|
mmu->mfsrin = kvmppc_mmu_book3s_32_mfsrin;
|
||
|
|
mmu->xlate = kvmppc_mmu_book3s_32_xlate;
|
||
|
|
mmu->reset_msr = kvmppc_mmu_book3s_32_reset_msr;
|
||
|
|
mmu->tlbie = kvmppc_mmu_book3s_32_tlbie;
|
||
|
|
mmu->esid_to_vsid = kvmppc_mmu_book3s_32_esid_to_vsid;
|
||
|
|
mmu->ea_to_vp = kvmppc_mmu_book3s_32_ea_to_vp;
|
||
|
|
mmu->is_dcbz32 = kvmppc_mmu_book3s_32_is_dcbz32;
|
||
|
|
|
||
|
|
mmu->slbmte = NULL;
|
||
|
|
mmu->slbmfee = NULL;
|
||
|
|
mmu->slbmfev = NULL;
|
||
|
|
mmu->slbfee = NULL;
|
||
|
|
mmu->slbie = NULL;
|
||
|
|
mmu->slbia = NULL;
|
||
|
|
}
|