33 lines
785 B
C
33 lines
785 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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/* The synchronize caches instruction executes as a nop on systems in
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which all memory references are performed in order. */
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#define synchronize_caches() __asm__ __volatile__ ("sync" : : : "memory")
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#if defined(CONFIG_SMP)
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#define mb() do { synchronize_caches(); } while (0)
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#define rmb() mb()
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#define wmb() mb()
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#define dma_rmb() mb()
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#define dma_wmb() mb()
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#else
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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#endif
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#define __smp_mb() mb()
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#define __smp_rmb() mb()
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#define __smp_wmb() mb()
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#include <asm-generic/barrier.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_BARRIER_H */
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