252 lines
8.6 KiB
C
252 lines
8.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Ralink RT3662/RT3883 SoC register definitions
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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*/
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#ifndef _RT3883_REGS_H_
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#define _RT3883_REGS_H_
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#include <linux/bitops.h>
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#define RT3883_SDRAM_BASE 0x00000000
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#define RT3883_SYSC_BASE 0x10000000
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#define RT3883_TIMER_BASE 0x10000100
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#define RT3883_INTC_BASE 0x10000200
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#define RT3883_MEMC_BASE 0x10000300
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#define RT3883_UART0_BASE 0x10000500
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#define RT3883_PIO_BASE 0x10000600
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#define RT3883_FSCC_BASE 0x10000700
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#define RT3883_NANDC_BASE 0x10000810
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#define RT3883_I2C_BASE 0x10000900
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#define RT3883_I2S_BASE 0x10000a00
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#define RT3883_SPI_BASE 0x10000b00
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#define RT3883_UART1_BASE 0x10000c00
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#define RT3883_PCM_BASE 0x10002000
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#define RT3883_GDMA_BASE 0x10002800
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#define RT3883_CODEC1_BASE 0x10003000
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#define RT3883_CODEC2_BASE 0x10003800
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#define RT3883_FE_BASE 0x10100000
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#define RT3883_ROM_BASE 0x10118000
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#define RT3883_USBDEV_BASE 0x10112000
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#define RT3883_PCI_BASE 0x10140000
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#define RT3883_WLAN_BASE 0x10180000
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#define RT3883_USBHOST_BASE 0x101c0000
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#define RT3883_BOOT_BASE 0x1c000000
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#define RT3883_SRAM_BASE 0x1e000000
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#define RT3883_PCIMEM_BASE 0x20000000
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#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
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#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
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#define RT3883_SYSC_SIZE 0x100
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#define RT3883_TIMER_SIZE 0x100
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#define RT3883_INTC_SIZE 0x100
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#define RT3883_MEMC_SIZE 0x100
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#define RT3883_UART0_SIZE 0x100
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#define RT3883_UART1_SIZE 0x100
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#define RT3883_PIO_SIZE 0x100
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#define RT3883_FSCC_SIZE 0x100
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#define RT3883_NANDC_SIZE 0x0f0
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#define RT3883_I2C_SIZE 0x100
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#define RT3883_I2S_SIZE 0x100
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#define RT3883_SPI_SIZE 0x100
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#define RT3883_PCM_SIZE 0x800
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#define RT3883_GDMA_SIZE 0x800
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#define RT3883_CODEC1_SIZE 0x800
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#define RT3883_CODEC2_SIZE 0x800
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#define RT3883_FE_SIZE 0x10000
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#define RT3883_ROM_SIZE 0x4000
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#define RT3883_USBDEV_SIZE 0x4000
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#define RT3883_PCI_SIZE 0x40000
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#define RT3883_WLAN_SIZE 0x40000
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#define RT3883_USBHOST_SIZE 0x40000
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#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
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#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
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/* SYSC registers */
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#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
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#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
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#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
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#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
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#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
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#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
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#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
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#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
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#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
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#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
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#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
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#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
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#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
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#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
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#define RT3883_SYSC_REG_PMU 0x88
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#define RT3883_SYSC_REG_PMU1 0x8c
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#define RT3883_CHIP_NAME0 0x38335452
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#define RT3883_CHIP_NAME1 0x20203338
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#define RT3883_REVID_VER_ID_MASK 0x0f
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#define RT3883_REVID_VER_ID_SHIFT 8
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#define RT3883_REVID_ECO_ID_MASK 0x0f
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#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
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#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
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#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
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#define RT3883_SYSCFG0_CPUCLK_250 0x0
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#define RT3883_SYSCFG0_CPUCLK_384 0x1
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#define RT3883_SYSCFG0_CPUCLK_480 0x2
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#define RT3883_SYSCFG0_CPUCLK_500 0x3
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#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
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#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
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#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
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#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
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#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
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#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
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#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
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#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
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#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
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#define RT3883_GPIO_MODE_UART0_SHIFT 2
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#define RT3883_GPIO_MODE_UART0_MASK 0x7
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#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
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#define RT3883_GPIO_MODE_UARTF 0x0
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#define RT3883_GPIO_MODE_PCM_UARTF 0x1
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#define RT3883_GPIO_MODE_PCM_I2S 0x2
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#define RT3883_GPIO_MODE_I2S_UARTF 0x3
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#define RT3883_GPIO_MODE_PCM_GPIO 0x4
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#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
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#define RT3883_GPIO_MODE_GPIO_I2S 0x6
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#define RT3883_GPIO_MODE_GPIO 0x7
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#define RT3883_GPIO_MODE_I2C 0
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#define RT3883_GPIO_MODE_SPI 1
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#define RT3883_GPIO_MODE_UART1 5
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#define RT3883_GPIO_MODE_JTAG 6
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#define RT3883_GPIO_MODE_MDIO 7
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#define RT3883_GPIO_MODE_GE1 9
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#define RT3883_GPIO_MODE_GE2 10
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#define RT3883_GPIO_MODE_PCI_SHIFT 11
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#define RT3883_GPIO_MODE_PCI_MASK 0x7
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#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
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#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
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#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
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#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
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#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
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#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
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#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
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#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
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#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
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#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
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#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
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#define RT3883_GPIO_I2C_SD 1
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#define RT3883_GPIO_I2C_SCLK 2
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#define RT3883_GPIO_SPI_CS0 3
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#define RT3883_GPIO_SPI_CLK 4
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#define RT3883_GPIO_SPI_MOSI 5
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#define RT3883_GPIO_SPI_MISO 6
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#define RT3883_GPIO_7 7
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#define RT3883_GPIO_10 10
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#define RT3883_GPIO_11 11
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#define RT3883_GPIO_14 14
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#define RT3883_GPIO_UART1_TXD 15
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#define RT3883_GPIO_UART1_RXD 16
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#define RT3883_GPIO_JTAG_TDO 17
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#define RT3883_GPIO_JTAG_TDI 18
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#define RT3883_GPIO_JTAG_TMS 19
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#define RT3883_GPIO_JTAG_TCLK 20
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#define RT3883_GPIO_JTAG_TRST_N 21
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#define RT3883_GPIO_MDIO_MDC 22
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#define RT3883_GPIO_MDIO_MDIO 23
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#define RT3883_GPIO_LNA_PE_A0 32
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#define RT3883_GPIO_LNA_PE_A1 33
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#define RT3883_GPIO_LNA_PE_A2 34
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#define RT3883_GPIO_LNA_PE_G0 35
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#define RT3883_GPIO_LNA_PE_G1 36
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#define RT3883_GPIO_LNA_PE_G2 37
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#define RT3883_GPIO_PCI_AD0 40
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#define RT3883_GPIO_PCI_AD31 71
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#define RT3883_GPIO_GE2_TXD0 72
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#define RT3883_GPIO_GE2_TXD1 73
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#define RT3883_GPIO_GE2_TXD2 74
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#define RT3883_GPIO_GE2_TXD3 75
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#define RT3883_GPIO_GE2_TXEN 76
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#define RT3883_GPIO_GE2_TXCLK 77
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#define RT3883_GPIO_GE2_RXD0 78
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#define RT3883_GPIO_GE2_RXD1 79
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#define RT3883_GPIO_GE2_RXD2 80
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#define RT3883_GPIO_GE2_RXD3 81
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#define RT3883_GPIO_GE2_RXDV 82
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#define RT3883_GPIO_GE2_RXCLK 83
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#define RT3883_GPIO_GE1_TXD0 84
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#define RT3883_GPIO_GE1_TXD1 85
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#define RT3883_GPIO_GE1_TXD2 86
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#define RT3883_GPIO_GE1_TXD3 87
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#define RT3883_GPIO_GE1_TXEN 88
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#define RT3883_GPIO_GE1_TXCLK 89
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#define RT3883_GPIO_GE1_RXD0 90
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#define RT3883_GPIO_GE1_RXD1 91
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#define RT3883_GPIO_GE1_RXD2 92
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#define RT3883_GPIO_GE1_RXD3 93
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#define RT3883_GPIO_GE1_RXDV 94
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#define RT3883_GPIO_GE1_RXCLK 95
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#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
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#define RT3883_RSTCTRL_FLASH BIT(26)
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#define RT3883_RSTCTRL_UDEV BIT(25)
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#define RT3883_RSTCTRL_PCI BIT(24)
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#define RT3883_RSTCTRL_PCIE BIT(23)
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#define RT3883_RSTCTRL_UHST BIT(22)
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#define RT3883_RSTCTRL_FE BIT(21)
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#define RT3883_RSTCTRL_WLAN BIT(20)
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#define RT3883_RSTCTRL_UART1 BIT(29)
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#define RT3883_RSTCTRL_SPI BIT(18)
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#define RT3883_RSTCTRL_I2S BIT(17)
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#define RT3883_RSTCTRL_I2C BIT(16)
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#define RT3883_RSTCTRL_NAND BIT(15)
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#define RT3883_RSTCTRL_DMA BIT(14)
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#define RT3883_RSTCTRL_PIO BIT(13)
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#define RT3883_RSTCTRL_UART BIT(12)
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#define RT3883_RSTCTRL_PCM BIT(11)
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#define RT3883_RSTCTRL_MC BIT(10)
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#define RT3883_RSTCTRL_INTC BIT(9)
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#define RT3883_RSTCTRL_TIMER BIT(8)
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#define RT3883_RSTCTRL_SYS BIT(0)
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#define RT3883_INTC_INT_SYSCTL BIT(0)
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#define RT3883_INTC_INT_TIMER0 BIT(1)
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#define RT3883_INTC_INT_TIMER1 BIT(2)
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#define RT3883_INTC_INT_IA BIT(3)
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#define RT3883_INTC_INT_PCM BIT(4)
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#define RT3883_INTC_INT_UART0 BIT(5)
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#define RT3883_INTC_INT_PIO BIT(6)
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#define RT3883_INTC_INT_DMA BIT(7)
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#define RT3883_INTC_INT_NAND BIT(8)
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#define RT3883_INTC_INT_PERFC BIT(9)
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#define RT3883_INTC_INT_I2S BIT(10)
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#define RT3883_INTC_INT_UART1 BIT(12)
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#define RT3883_INTC_INT_UHST BIT(18)
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#define RT3883_INTC_INT_UDEV BIT(19)
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/* FLASH/SRAM/Codec Controller registers */
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#define RT3883_FSCC_REG_FLASH_CFG0 0x00
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#define RT3883_FSCC_REG_FLASH_CFG1 0x04
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#define RT3883_FSCC_REG_CODEC_CFG0 0x40
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#define RT3883_FSCC_REG_CODEC_CFG1 0x44
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#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
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#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
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#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
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#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
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#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
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#define RT3883_SDRAM_BASE 0x00000000
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#define RT3883_MEM_SIZE_MIN 2
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#define RT3883_MEM_SIZE_MAX 256
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#endif /* _RT3883_REGS_H_ */
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