588 lines
13 KiB
Plaintext
588 lines
13 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,bcm7425";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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mips-hpt-frequency = <163125000>;
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cpu@0 {
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compatible = "brcm,bmips5000";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "brcm,bmips5000";
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device_type = "cpu";
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reg = <1>;
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};
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};
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aliases {
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uart0 = &uart0;
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};
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cpu_intc: interrupt-controller {
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#address-cells = <0>;
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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clocks {
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uart_clk: uart_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <81000000>;
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};
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upg_clk: upg_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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rdb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x10000000 0x01000000>;
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periph_intc: interrupt-controller@41a400 {
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compatible = "brcm,bcm7038-l1-intc";
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reg = <0x41a400 0x30>, <0x41a600 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>, <3>;
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};
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sun_l2_intc: interrupt-controller@403000 {
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compatible = "brcm,l2-intc";
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reg = <0x403000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <47>;
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};
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gisb-arb@400000 {
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compatible = "brcm,bcm7400-gisb-arb";
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reg = <0x400000 0xdc>;
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native-endian;
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interrupt-parent = <&sun_l2_intc>;
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interrupts = <0>, <2>;
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brcm,gisb-arb-master-mask = <0x177b>;
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brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
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"bsp_0", "rdc_0",
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"raaga_0", "avd_1",
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"jtag_0", "svd_0",
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"vice_0";
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};
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upg_irq0_intc: interrupt-controller@406780 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x406780 0x8>;
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brcm,int-map-mask = <0x44>, <0x7000000>;
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brcm,int-fwd-mask = <0x70000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <55>, <53>;
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interrupt-names = "upg_main", "upg_bsc";
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};
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upg_aon_irq0_intc: interrupt-controller@409480 {
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x409480 0x8>;
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brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
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brcm,int-fwd-mask = <0>;
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brcm,irq-can-wake;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <56>, <54>, <59>;
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interrupt-names = "upg_main_aon", "upg_bsc_aon",
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"upg_spi";
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};
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sun_top_ctrl: syscon@404000 {
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compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
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reg = <0x404000 0x51c>;
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native-endian;
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};
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reboot {
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compatible = "brcm,brcmstb-reboot";
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syscon = <&sun_top_ctrl 0x304 0x308>;
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};
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uart0: serial@406b00 {
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compatible = "ns16550a";
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reg = <0x406b00 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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interrupt-parent = <&periph_intc>;
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interrupts = <61>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@406b40 {
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compatible = "ns16550a";
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reg = <0x406b40 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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interrupt-parent = <&periph_intc>;
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interrupts = <62>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@406b80 {
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compatible = "ns16550a";
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reg = <0x406b80 0x20>;
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reg-io-width = <0x4>;
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reg-shift = <0x2>;
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interrupt-parent = <&periph_intc>;
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interrupts = <63>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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bsca: i2c@409180 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_aon_irq0_intc>;
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reg = <0x409180 0x58>;
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interrupts = <27>;
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interrupt-names = "upg_bsca";
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status = "disabled";
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};
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bscb: i2c@409400 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_aon_irq0_intc>;
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reg = <0x409400 0x58>;
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interrupts = <28>;
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interrupt-names = "upg_bscb";
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status = "disabled";
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};
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bscc: i2c@406200 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406200 0x58>;
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interrupts = <24>;
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interrupt-names = "upg_bscc";
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status = "disabled";
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};
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bscd: i2c@406280 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406280 0x58>;
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interrupts = <25>;
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interrupt-names = "upg_bscd";
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status = "disabled";
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};
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bsce: i2c@406300 {
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clock-frequency = <390000>;
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compatible = "brcm,brcmstb-i2c";
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interrupt-parent = <&upg_irq0_intc>;
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reg = <0x406300 0x58>;
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interrupts = <26>;
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interrupt-names = "upg_bsce";
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status = "disabled";
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};
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pwma: pwm@406580 {
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compatible = "brcm,bcm7038-pwm";
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reg = <0x406580 0x28>;
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#pwm-cells = <2>;
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clocks = <&upg_clk>;
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status = "disabled";
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};
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pwmb: pwm@406800 {
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compatible = "brcm,bcm7038-pwm";
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reg = <0x406800 0x28>;
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#pwm-cells = <2>;
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clocks = <&upg_clk>;
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status = "disabled";
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};
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watchdog: watchdog@4067e8 {
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clocks = <&upg_clk>;
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compatible = "brcm,bcm7038-wdt";
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reg = <0x4067e8 0x14>;
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status = "disabled";
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};
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aon_pm_l2_intc: interrupt-controller@408440 {
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compatible = "brcm,l2-intc";
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reg = <0x408440 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <49>;
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brcm,irq-can-wake;
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};
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aon_ctrl: syscon@408000 {
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compatible = "brcm,brcmstb-aon-ctrl";
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reg = <0x408000 0x100>, <0x408200 0x200>;
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reg-names = "aon-ctrl", "aon-sram";
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};
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timers: timer@4067c0 {
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compatible = "brcm,brcmstb-timers";
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reg = <0x4067c0 0x40>;
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};
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upg_gio: gpio@406700 {
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compatible = "brcm,brcmstb-gpio";
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reg = <0x406700 0x80>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&upg_irq0_intc>;
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interrupts = <6>;
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brcm,gpio-bank-widths = <32 32 32 21>;
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};
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upg_gio_aon: gpio@4094c0 {
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compatible = "brcm,brcmstb-gpio";
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reg = <0x4094c0 0x40>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupts = <6>;
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interrupts-extended = <&upg_aon_irq0_intc 6>,
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<&aon_pm_l2_intc 5>;
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wakeup-source;
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brcm,gpio-bank-widths = <18 4>;
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};
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enet0: ethernet@b80000 {
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phy-mode = "internal";
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phy-handle = <&phy1>;
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mac-address = [ 00 10 18 36 23 1a ];
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compatible = "brcm,genet-v3";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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reg = <0xb80000 0x11c88>;
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interrupts = <17>, <18>;
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interrupt-parent = <&periph_intc>;
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status = "disabled";
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mdio@e14 {
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compatible = "brcm,genet-mdio-v3";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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reg = <0xe14 0x8>;
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phy1: ethernet-phy@1 {
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max-speed = <100>;
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reg = <0x1>;
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compatible = "brcm,40nm-ephy",
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"ethernet-phy-ieee802.3-c22";
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};
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};
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};
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ehci0: usb@480300 {
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compatible = "brcm,bcm7425-ehci", "generic-ehci";
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reg = <0x480300 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <65>;
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status = "disabled";
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};
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ohci0: usb@480400 {
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compatible = "brcm,bcm7425-ohci", "generic-ohci";
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reg = <0x480400 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <67>;
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status = "disabled";
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};
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ehci1: usb@480500 {
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compatible = "brcm,bcm7425-ehci", "generic-ehci";
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reg = <0x480500 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <66>;
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status = "disabled";
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};
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ohci1: usb@480600 {
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compatible = "brcm,bcm7425-ohci", "generic-ohci";
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reg = <0x480600 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <68>;
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status = "disabled";
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};
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ehci2: usb@490300 {
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compatible = "brcm,bcm7425-ehci", "generic-ehci";
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reg = <0x490300 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
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interrupts = <70>;
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status = "disabled";
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};
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ohci2: usb@490400 {
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compatible = "brcm,bcm7425-ohci", "generic-ohci";
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reg = <0x490400 0x100>;
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native-endian;
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no-big-frame-no;
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interrupt-parent = <&periph_intc>;
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interrupts = <72>;
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status = "disabled";
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};
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ehci3: usb@490500 {
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compatible = "brcm,bcm7425-ehci", "generic-ehci";
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reg = <0x490500 0x100>;
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native-endian;
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interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <71>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ohci3: usb@490600 {
|
||
|
|
compatible = "brcm,bcm7425-ohci", "generic-ohci";
|
||
|
|
reg = <0x490600 0x100>;
|
||
|
|
native-endian;
|
||
|
|
no-big-frame-no;
|
||
|
|
interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <73>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
hif_l2_intc: interrupt-controller@41a000 {
|
||
|
|
compatible = "brcm,l2-intc";
|
||
|
|
reg = <0x41a000 0x30>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <24>;
|
||
|
|
};
|
||
|
|
|
||
|
|
nand: nand@41b800 {
|
||
|
|
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
reg-names = "nand";
|
||
|
|
reg = <0x41b800 0x400>;
|
||
|
|
interrupt-parent = <&hif_l2_intc>;
|
||
|
|
interrupts = <24>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sata: sata@181000 {
|
||
|
|
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
|
||
|
|
reg-names = "ahci", "top-ctrl";
|
||
|
|
reg = <0x181000 0xa9c>, <0x180020 0x1c>;
|
||
|
|
interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <41>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
sata0: sata-port@0 {
|
||
|
|
reg = <0>;
|
||
|
|
phys = <&sata_phy0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sata1: sata-port@1 {
|
||
|
|
reg = <1>;
|
||
|
|
phys = <&sata_phy1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sata_phy: sata-phy@180100 {
|
||
|
|
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
|
||
|
|
reg = <0x180100 0x0eff>;
|
||
|
|
reg-names = "phy";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
sata_phy0: sata-phy@0 {
|
||
|
|
reg = <0>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sata_phy1: sata-phy@1 {
|
||
|
|
reg = <1>;
|
||
|
|
#phy-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhci0: sdhci@419000 {
|
||
|
|
compatible = "brcm,bcm7425-sdhci";
|
||
|
|
reg = <0x419000 0x100>;
|
||
|
|
interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <43>;
|
||
|
|
sd-uhs-sdr50;
|
||
|
|
mmc-hs200-1_8v;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhci1: sdhci@419200 {
|
||
|
|
compatible = "brcm,bcm7425-sdhci";
|
||
|
|
reg = <0x419200 0x100>;
|
||
|
|
interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <44>;
|
||
|
|
sd-uhs-sdr50;
|
||
|
|
mmc-hs200-1_8v;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi_l2_intc: interrupt-controller@41ad00 {
|
||
|
|
compatible = "brcm,l2-intc";
|
||
|
|
reg = <0x41ad00 0x30>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-parent = <&periph_intc>;
|
||
|
|
interrupts = <25>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qspi: spi@41c000 {
|
||
|
|
#address-cells = <0x1>;
|
||
|
|
#size-cells = <0x0>;
|
||
|
|
compatible = "brcm,spi-bcm-qspi",
|
||
|
|
"brcm,spi-brcmstb-qspi";
|
||
|
|
clocks = <&upg_clk>;
|
||
|
|
reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
|
||
|
|
reg-names = "cs_reg", "hif_mspi", "bspi";
|
||
|
|
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
|
||
|
|
interrupt-parent = <&spi_l2_intc>;
|
||
|
|
interrupt-names = "spi_lr_fullness_reached",
|
||
|
|
"spi_lr_session_aborted",
|
||
|
|
"spi_lr_impatient",
|
||
|
|
"spi_lr_session_done",
|
||
|
|
"spi_lr_overread",
|
||
|
|
"mspi_done",
|
||
|
|
"mspi_halted";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
mspi: spi@409200 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "brcm,spi-bcm-qspi",
|
||
|
|
"brcm,spi-brcmstb-mspi";
|
||
|
|
clocks = <&upg_clk>;
|
||
|
|
reg = <0x409200 0x180>;
|
||
|
|
reg-names = "mspi";
|
||
|
|
interrupts = <0x14>;
|
||
|
|
interrupt-parent = <&upg_aon_irq0_intc>;
|
||
|
|
interrupt-names = "mspi_done";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
waketimer: waketimer@409580 {
|
||
|
|
compatible = "brcm,brcmstb-waketimer";
|
||
|
|
reg = <0x409580 0x14>;
|
||
|
|
interrupts = <0x3>;
|
||
|
|
interrupt-parent = <&aon_pm_l2_intc>;
|
||
|
|
interrupt-names = "timer";
|
||
|
|
clocks = <&upg_clk>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
memory_controllers {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
ranges = <0x0 0x103b0000 0x1a000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
memory-controller@0 {
|
||
|
|
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||
|
|
ranges = <0x0 0x0 0xa000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
memc-arb@1000 {
|
||
|
|
compatible = "brcm,brcmstb-memc-arb";
|
||
|
|
reg = <0x1000 0x248>;
|
||
|
|
};
|
||
|
|
|
||
|
|
memc-ddr@2000 {
|
||
|
|
compatible = "brcm,brcmstb-memc-ddr";
|
||
|
|
reg = <0x2000 0x300>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ddr-phy@6000 {
|
||
|
|
compatible = "brcm,brcmstb-ddr-phy";
|
||
|
|
reg = <0x6000 0xc8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
shimphy@8000 {
|
||
|
|
compatible = "brcm,brcmstb-ddr-shimphy";
|
||
|
|
reg = <0x8000 0x13c>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
memory-controller@1 {
|
||
|
|
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||
|
|
ranges = <0x0 0x10000 0xa000>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
memc-arb@1000 {
|
||
|
|
compatible = "brcm,brcmstb-memc-arb";
|
||
|
|
reg = <0x1000 0x248>;
|
||
|
|
};
|
||
|
|
|
||
|
|
memc-ddr@2000 {
|
||
|
|
compatible = "brcm,brcmstb-memc-ddr";
|
||
|
|
reg = <0x2000 0x300>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ddr-phy@6000 {
|
||
|
|
compatible = "brcm,brcmstb-ddr-phy";
|
||
|
|
reg = <0x6000 0xc8>;
|
||
|
|
};
|
||
|
|
|
||
|
|
shimphy@8000 {
|
||
|
|
compatible = "brcm,brcmstb-ddr-shimphy";
|
||
|
|
reg = <0x8000 0x13c>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|