187 lines
2.6 KiB
C
187 lines
2.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_ENTRY_H
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#define __ASM_CSKY_ENTRY_H
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#include <asm/setup.h>
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#include <abi/regdef.h>
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#define LSAVE_PC 8
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#define LSAVE_PSR 12
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#define LSAVE_A0 24
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#define LSAVE_A1 28
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#define LSAVE_A2 32
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#define LSAVE_A3 36
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#define LSAVE_A4 40
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#define LSAVE_A5 44
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#define usp ss1
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.macro USPTOKSP
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mtcr sp, usp
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mfcr sp, ss0
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.endm
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.macro KSPTOUSP
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mtcr sp, ss0
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mfcr sp, usp
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.endm
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.macro SAVE_ALL epc_inc
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mtcr r13, ss2
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mfcr r13, epsr
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btsti r13, 31
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bt 1f
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USPTOKSP
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1:
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subi sp, 32
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subi sp, 32
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subi sp, 16
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stw r13, (sp, 12)
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stw lr, (sp, 4)
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mfcr lr, epc
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movi r13, \epc_inc
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add lr, r13
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stw lr, (sp, 8)
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mov lr, sp
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addi lr, 32
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addi lr, 32
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addi lr, 16
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bt 2f
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mfcr lr, ss1
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2:
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stw lr, (sp, 16)
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stw a0, (sp, 20)
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stw a0, (sp, 24)
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stw a1, (sp, 28)
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stw a2, (sp, 32)
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stw a3, (sp, 36)
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addi sp, 32
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addi sp, 8
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mfcr r13, ss2
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stw r6, (sp)
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stw r7, (sp, 4)
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stw r8, (sp, 8)
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stw r9, (sp, 12)
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stw r10, (sp, 16)
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stw r11, (sp, 20)
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stw r12, (sp, 24)
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stw r13, (sp, 28)
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stw r14, (sp, 32)
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stw r1, (sp, 36)
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subi sp, 32
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subi sp, 8
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.endm
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.macro RESTORE_ALL
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psrclr ie
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ldw lr, (sp, 4)
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ldw a0, (sp, 8)
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mtcr a0, epc
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ldw a0, (sp, 12)
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mtcr a0, epsr
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btsti a0, 31
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bt 1f
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ldw a0, (sp, 16)
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mtcr a0, ss1
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1:
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ldw a0, (sp, 24)
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ldw a1, (sp, 28)
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ldw a2, (sp, 32)
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ldw a3, (sp, 36)
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addi sp, 32
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addi sp, 8
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ldw r6, (sp)
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ldw r7, (sp, 4)
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ldw r8, (sp, 8)
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ldw r9, (sp, 12)
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ldw r10, (sp, 16)
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ldw r11, (sp, 20)
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ldw r12, (sp, 24)
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ldw r13, (sp, 28)
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ldw r14, (sp, 32)
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ldw r1, (sp, 36)
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addi sp, 32
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addi sp, 8
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bt 2f
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KSPTOUSP
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2:
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rte
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.endm
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.macro SAVE_SWITCH_STACK
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subi sp, 32
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stm r8-r15, (sp)
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.endm
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.macro RESTORE_SWITCH_STACK
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ldm r8-r15, (sp)
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addi sp, 32
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.endm
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/* MMU registers operators. */
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.macro RD_MIR rx
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cprcr \rx, cpcr0
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.endm
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.macro RD_MEH rx
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cprcr \rx, cpcr4
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.endm
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.macro RD_MCIR rx
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cprcr \rx, cpcr8
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.endm
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.macro RD_PGDR rx
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cprcr \rx, cpcr29
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.endm
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.macro WR_MEH rx
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cpwcr \rx, cpcr4
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.endm
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.macro WR_MCIR rx
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cpwcr \rx, cpcr8
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.endm
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.macro SETUP_MMU
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/* Init psr and enable ee */
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lrw r6, DEFAULT_PSR_VALUE
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mtcr r6, psr
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psrset ee
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/* Select MMU as co-processor */
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cpseti cp15
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/*
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* cpcr30 format:
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* 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0
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* BA Reserved C D V
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*/
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cprcr r6, cpcr30
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lsri r6, 28
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lsli r6, 28
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addi r6, 0xe
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cpwcr r6, cpcr30
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lsri r6, 28
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addi r6, 2
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lsli r6, 28
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addi r6, 0xe
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cpwcr r6, cpcr31
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.endm
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.macro ANDI_R3 rx, imm
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lsri \rx, 3
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andi \rx, (\imm >> 3)
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.endm
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#endif /* __ASM_CSKY_ENTRY_H */
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