272 lines
6.8 KiB
ArmAsm
272 lines
6.8 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2012 Linaro Limited.
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*/
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#include <linux/init.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/virt.h>
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#ifndef ZIMAGE
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/*
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* For the kernel proper, we need to find out the CPU boot mode long after
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* boot, so we need to store it in a writable variable.
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*
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* This is not in .bss, because we set it sufficiently early that the boot-time
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* zeroing of .bss would clobber it.
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*/
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.data
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.align 2
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ENTRY(__boot_cpu_mode)
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.long 0
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.text
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/*
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* Save the primary CPU boot mode. Requires 3 scratch registers.
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*/
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.macro store_primary_cpu_mode reg1, reg2, reg3
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mrs \reg1, cpsr
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and \reg1, \reg1, #MODE_MASK
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adr \reg2, .L__boot_cpu_mode_offset
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ldr \reg3, [\reg2]
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str \reg1, [\reg2, \reg3]
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.endm
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/*
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* Compare the current mode with the one saved on the primary CPU.
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* If they don't match, record that fact. The Z bit indicates
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* if there's a match or not.
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* Requires 3 additionnal scratch registers.
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*/
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.macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
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adr \reg2, .L__boot_cpu_mode_offset
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ldr \reg3, [\reg2]
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ldr \reg1, [\reg2, \reg3]
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cmp \mode, \reg1 @ matches primary CPU boot mode?
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orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
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strne \reg1, [\reg2, \reg3] @ record what happened and give up
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.endm
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#else /* ZIMAGE */
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.macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
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.endm
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/*
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* The zImage loader only runs on one CPU, so we don't bother with mult-CPU
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* consistency checking:
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*/
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.macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
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cmp \mode, \mode
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.endm
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#endif /* ZIMAGE */
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/*
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* Hypervisor stub installation functions.
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*
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* These must be called with the MMU and D-cache off.
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* They are not ABI compliant and are only intended to be called from the kernel
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* entry points in head.S.
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*/
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@ Call this from the primary CPU
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ENTRY(__hyp_stub_install)
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store_primary_cpu_mode r4, r5, r6
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ENDPROC(__hyp_stub_install)
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@ fall through...
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@ Secondary CPUs should call here
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ENTRY(__hyp_stub_install_secondary)
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mrs r4, cpsr
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and r4, r4, #MODE_MASK
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/*
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* If the secondary has booted with a different mode, give up
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* immediately.
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*/
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compare_cpu_mode_with_primary r4, r5, r6, r7
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retne lr
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/*
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* Once we have given up on one CPU, we do not try to install the
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* stub hypervisor on the remaining ones: because the saved boot mode
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* is modified, it can't compare equal to the CPSR mode field any
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* more.
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*
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* Otherwise...
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*/
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cmp r4, #HYP_MODE
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retne lr @ give up if the CPU is not in HYP mode
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/*
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* Configure HSCTLR to set correct exception endianness/instruction set
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* state etc.
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* Turn off all traps
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* Eventually, CPU-specific code might be needed -- assume not for now
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*
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* This code relies on the "eret" instruction to synchronize the
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* various coprocessor accesses. This is done when we switch to SVC
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* (see safe_svcmode_maskall).
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*/
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@ Now install the hypervisor stub:
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W(adr) r7, __hyp_stub_vectors
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mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
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@ Disable all traps, so we don't get any nasty surprise
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mov r7, #0
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mcr p15, 4, r7, c1, c1, 0 @ HCR
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mcr p15, 4, r7, c1, c1, 2 @ HCPTR
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mcr p15, 4, r7, c1, c1, 3 @ HSTR
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THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
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ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
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mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
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mrc p15, 4, r7, c1, c1, 1 @ HDCR
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and r7, #0x1f @ Preserve HPMN
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mcr p15, 4, r7, c1, c1, 1 @ HDCR
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@ Make sure NS-SVC is initialised appropriately
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mrc p15, 0, r7, c1, c0, 0 @ SCTLR
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orr r7, #(1 << 5) @ CP15 barriers enabled
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bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
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bic r7, #(3 << 19) @ WXN and UWXN disabled
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mcr p15, 0, r7, c1, c0, 0 @ SCTLR
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mrc p15, 0, r7, c0, c0, 0 @ MIDR
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mcr p15, 4, r7, c0, c0, 0 @ VPIDR
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mrc p15, 0, r7, c0, c0, 5 @ MPIDR
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mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
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#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
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@ make CNTP_* and CNTPCT accessible from PL1
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mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
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ubfx r7, r7, #16, #4
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teq r7, #0
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beq 1f
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mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
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orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
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mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
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mov r7, #0
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mcrr p15, 4, r7, r7, c14 @ CNTVOFF
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@ Disable virtual timer in case it was counting
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mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
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bic r7, #1 @ Clear ENABLE
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mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
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1:
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#endif
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#ifdef CONFIG_ARM_GIC_V3
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@ Check whether GICv3 system registers are available
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mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
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ubfx r7, r7, #28, #4
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teq r7, #0
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beq 2f
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@ Enable system register accesses
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mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
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orr r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
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mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE
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isb
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@ SRE bit could be forced to 0 by firmware.
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@ Check whether it sticks before accessing any other sysreg
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mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
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tst r7, #ICC_SRE_EL2_SRE
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beq 2f
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mov r7, #0
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mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR
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2:
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#endif
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bx lr @ The boot CPU mode is left in r4.
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ENDPROC(__hyp_stub_install_secondary)
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__hyp_stub_do_trap:
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teq r0, #HVC_SET_VECTORS
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bne 1f
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mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
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b __hyp_stub_exit
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1: teq r0, #HVC_SOFT_RESTART
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bne 1f
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bx r1
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1: teq r0, #HVC_RESET_VECTORS
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beq __hyp_stub_exit
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ldr r0, =HVC_STUB_ERR
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__ERET
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__hyp_stub_exit:
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mov r0, #0
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__ERET
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ENDPROC(__hyp_stub_do_trap)
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/*
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* __hyp_set_vectors: Call this after boot to set the initial hypervisor
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* vectors as part of hypervisor installation. On an SMP system, this should
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* be called on each CPU.
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*
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* r0 must be the physical address of the new vector table (which must lie in
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* the bottom 4GB of physical address space.
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*
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* r0 must be 32-byte aligned.
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*
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* Before calling this, you must check that the stub hypervisor is installed
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* everywhere, by waiting for any secondary CPUs to be brought up and then
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* checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
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*
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* If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
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* something else went wrong... in such cases, trying to install a new
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* hypervisor is unlikely to work as desired.
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*
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* When you call into your shiny new hypervisor, sp_hyp will contain junk,
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* so you will need to set that to something sensible at the new hypervisor's
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* initialisation entry point.
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*/
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ENTRY(__hyp_set_vectors)
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mov r1, r0
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mov r0, #HVC_SET_VECTORS
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__HVC(0)
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ret lr
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ENDPROC(__hyp_set_vectors)
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ENTRY(__hyp_soft_restart)
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mov r1, r0
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mov r0, #HVC_SOFT_RESTART
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__HVC(0)
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ret lr
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ENDPROC(__hyp_soft_restart)
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ENTRY(__hyp_reset_vectors)
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mov r0, #HVC_RESET_VECTORS
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__HVC(0)
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ret lr
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ENDPROC(__hyp_reset_vectors)
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#ifndef ZIMAGE
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.align 2
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.L__boot_cpu_mode_offset:
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.long __boot_cpu_mode - .
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#endif
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.align 5
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ENTRY(__hyp_stub_vectors)
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__hyp_stub_reset: W(b) .
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__hyp_stub_und: W(b) .
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__hyp_stub_svc: W(b) .
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__hyp_stub_pabort: W(b) .
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__hyp_stub_dabort: W(b) .
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__hyp_stub_trap: W(b) __hyp_stub_do_trap
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__hyp_stub_irq: W(b) .
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__hyp_stub_fiq: W(b) .
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ENDPROC(__hyp_stub_vectors)
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