1998 lines
48 KiB
Plaintext
1998 lines
48 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&scmi0_clk CK_SCMI0_MPU>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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nvmem-cells = <&part_number_otp>;
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nvmem-cell-names = "part_number";
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#cooling-cells = <2>;
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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scmi_sram: sram@2ffff000 {
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compatible = "mmio-sram";
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reg = <0x2ffff000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2ffff000 0x1000>;
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scmi0_shm: scmi_shm@0 {
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reg = <0 0x80>;
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};
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scmi1_shm: scmi_shm@200 {
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reg = <0x200 0x80>;
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};
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};
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scmi0_mbox: mailbox-0 {
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#mbox-cells = <0>;
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compatible = "arm,smc-mbox";
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arm,func-id = <0x82002000>;
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};
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scmi1_mbox: mailbox-1 {
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#mbox-cells = <0>;
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compatible = "arm,smc-mbox";
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arm,func-id = <0x82002001>;
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};
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firmware {
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scmi0: scmi-0 {
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compatible = "arm,scmi";
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#address-cells = <1>;
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#size-cells = <0>;
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mboxes = <&scmi0_mbox 0>;
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mbox-names = "txrx";
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shmem = <&scmi0_shm>;
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scmi0_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi0_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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scmi1: scmi-1 {
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compatible = "arm,scmi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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mboxes = <&scmi1_mbox 0>;
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mbox-names = "txrx";
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shmem = <&scmi1_shm>;
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scmi1_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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status = "disabled";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&intc>;
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always-on;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&dts>;
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trips {
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cpu-crit {
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temperature = <120000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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};
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booster: regulator-booster {
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compatible = "st,stm32mp1-booster";
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st,syscfg = <&syscfg>;
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status = "disabled";
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};
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pm_domain {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32mp157c-pd";
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pd_core_ret: core-ret-power-domain@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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#power-domain-cells = <0>;
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label = "CORE-RETENTION";
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pd_core: core-power-domain@2 {
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reg = <2>;
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#power-domain-cells = <0>;
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label = "CORE";
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};
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};
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&rcc>;
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offset = <0x404>;
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mask = <0x1>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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sram: sram@10000000 {
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compatible = "mmio-sram";
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reg = <0x10000000 0x60000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10000000 0x60000>;
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};
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timers2: timer@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc TIM2_K>;
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clock-names = "int";
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dmas = <&dmamux1 18 0x400 0x80000001>,
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<&dmamux1 19 0x400 0x80000001>,
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<&dmamux1 20 0x400 0x80000001>,
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<&dmamux1 21 0x400 0x80000001>,
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<&dmamux1 22 0x400 0x80000001>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@1 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <1>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers3: timer@40001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc TIM3_K>;
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clock-names = "int";
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dmas = <&dmamux1 23 0x400 0x80000001>,
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<&dmamux1 24 0x400 0x80000001>,
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<&dmamux1 25 0x400 0x80000001>,
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<&dmamux1 26 0x400 0x80000001>,
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<&dmamux1 27 0x400 0x80000001>,
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<&dmamux1 28 0x400 0x80000001>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@2 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <2>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers4: timer@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc TIM4_K>;
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clock-names = "int";
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dmas = <&dmamux1 29 0x400 0x80000001>,
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<&dmamux1 30 0x400 0x80000001>,
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<&dmamux1 31 0x400 0x80000001>,
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<&dmamux1 32 0x400 0x80000001>;
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dma-names = "ch1", "ch2", "ch3", "ch4";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@3 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <3>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers5: timer@40003000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40003000 0x400>;
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clocks = <&rcc TIM5_K>;
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clock-names = "int";
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dmas = <&dmamux1 55 0x400 0x80000001>,
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<&dmamux1 56 0x400 0x80000001>,
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<&dmamux1 57 0x400 0x80000001>,
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<&dmamux1 58 0x400 0x80000001>,
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<&dmamux1 59 0x400 0x80000001>,
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<&dmamux1 60 0x400 0x80000001>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@4 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <4>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers6: timer@40004000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40004000 0x400>;
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clocks = <&rcc TIM6_K>;
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clock-names = "int";
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dmas = <&dmamux1 69 0x400 0x80000001>;
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dma-names = "up";
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status = "disabled";
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timer@5 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <5>;
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status = "disabled";
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};
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};
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timers7: timer@40005000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40005000 0x400>;
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clocks = <&rcc TIM7_K>;
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clock-names = "int";
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dmas = <&dmamux1 70 0x400 0x80000001>;
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dma-names = "up";
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status = "disabled";
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timer@6 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <6>;
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status = "disabled";
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};
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};
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timers12: timer@40006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40006000 0x400>;
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clocks = <&rcc TIM12_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@11 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <11>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timers13: timer@40007000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x40007000 0x400>;
|
||
|
|
clocks = <&rcc TIM13_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@12 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <12>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timers14: timer@40008000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x40008000 0x400>;
|
||
|
|
clocks = <&rcc TIM14_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@13 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <13>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
lptimer1: timer@40009000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-lptimer";
|
||
|
|
reg = <0x40009000 0x400>;
|
||
|
|
clocks = <&rcc LPTIM1_K>;
|
||
|
|
clock-names = "mux";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm-lp";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
trigger@0 {
|
||
|
|
compatible = "st,stm32-lptimer-trigger";
|
||
|
|
reg = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
counter {
|
||
|
|
compatible = "st,stm32-lptimer-counter";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
spi2: spi@4000b000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x4000b000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI2_K>;
|
||
|
|
resets = <&rcc SPI2_R>;
|
||
|
|
dmas = <&dmamux1 39 0x400 0x01>,
|
||
|
|
<&dmamux1 40 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2s2: audio-controller@4000b000 {
|
||
|
|
compatible = "st,stm32h7-i2s";
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
reg = <0x4000b000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 39 0x400 0x01>,
|
||
|
|
<&dmamux1 40 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi3: spi@4000c000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x4000c000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI3_K>;
|
||
|
|
resets = <&rcc SPI3_R>;
|
||
|
|
dmas = <&dmamux1 61 0x400 0x01>,
|
||
|
|
<&dmamux1 62 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2s3: audio-controller@4000c000 {
|
||
|
|
compatible = "st,stm32h7-i2s";
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
reg = <0x4000c000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 61 0x400 0x01>,
|
||
|
|
<&dmamux1 62 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spdifrx: audio-controller@4000d000 {
|
||
|
|
compatible = "st,stm32h7-spdifrx";
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
reg = <0x4000d000 0x400>;
|
||
|
|
clocks = <&rcc SPDIF_K>;
|
||
|
|
clock-names = "kclk";
|
||
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 93 0x400 0x01>,
|
||
|
|
<&dmamux1 94 0x400 0x01>;
|
||
|
|
dma-names = "rx", "rx-ctrl";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usart2: serial@4000e000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x4000e000 0x400>;
|
||
|
|
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc USART2_K>;
|
||
|
|
resets = <&rcc USART2_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 43 0x400 0x5>,
|
||
|
|
<&dmamux1 44 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usart3: serial@4000f000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x4000f000 0x400>;
|
||
|
|
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc USART3_K>;
|
||
|
|
resets = <&rcc USART3_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 45 0x400 0x5>,
|
||
|
|
<&dmamux1 46 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart4: serial@40010000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x40010000 0x400>;
|
||
|
|
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc UART4_K>;
|
||
|
|
resets = <&rcc UART4_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 63 0x400 0x5>,
|
||
|
|
<&dmamux1 64 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart5: serial@40011000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x40011000 0x400>;
|
||
|
|
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc UART5_K>;
|
||
|
|
resets = <&rcc UART5_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 65 0x400 0x5>,
|
||
|
|
<&dmamux1 66 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1: i2c@40012000 {
|
||
|
|
compatible = "st,stm32mp15-i2c";
|
||
|
|
reg = <0x40012000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C1_K>;
|
||
|
|
resets = <&rcc I2C1_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 33 0x400 0x80000001>,
|
||
|
|
<&dmamux1 34 0x400 0x80000001>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x1>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@40013000 {
|
||
|
|
compatible = "st,stm32mp15-i2c";
|
||
|
|
reg = <0x40013000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C2_K>;
|
||
|
|
resets = <&rcc I2C2_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 35 0x400 0x80000001>,
|
||
|
|
<&dmamux1 36 0x400 0x80000001>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x2>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3: i2c@40014000 {
|
||
|
|
compatible = "st,stm32mp15-i2c";
|
||
|
|
reg = <0x40014000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C3_K>;
|
||
|
|
resets = <&rcc I2C3_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 73 0x400 0x80000001>,
|
||
|
|
<&dmamux1 74 0x400 0x80000001>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x4>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c5: i2c@40015000 {
|
||
|
|
compatible = "st,stm32mp15-i2c";
|
||
|
|
reg = <0x40015000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc I2C5_K>;
|
||
|
|
resets = <&rcc I2C5_R>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&dmamux1 115 0x400 0x80000001>,
|
||
|
|
<&dmamux1 116 0x400 0x80000001>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x10>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
cec: cec@40016000 {
|
||
|
|
compatible = "st,stm32-cec";
|
||
|
|
reg = <0x40016000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>;
|
||
|
|
clock-names = "cec", "hdmi-cec";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dac: dac@40017000 {
|
||
|
|
compatible = "st,stm32h7-dac-core";
|
||
|
|
reg = <0x40017000 0x400>;
|
||
|
|
clocks = <&rcc DAC12>;
|
||
|
|
clock-names = "pclk";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
dac1: dac@1 {
|
||
|
|
compatible = "st,stm32-dac";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dac2: dac@2 {
|
||
|
|
compatible = "st,stm32-dac";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
uart7: serial@40018000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x40018000 0x400>;
|
||
|
|
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc UART7_K>;
|
||
|
|
resets = <&rcc UART7_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 79 0x400 0x5>,
|
||
|
|
<&dmamux1 80 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart8: serial@40019000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x40019000 0x400>;
|
||
|
|
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc UART8_K>;
|
||
|
|
resets = <&rcc UART8_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 81 0x400 0x5>,
|
||
|
|
<&dmamux1 82 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timers1: timer@44000000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x44000000 0x400>;
|
||
|
|
clocks = <&rcc TIM1_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
dmas = <&dmamux1 11 0x400 0x80000001>,
|
||
|
|
<&dmamux1 12 0x400 0x80000001>,
|
||
|
|
<&dmamux1 13 0x400 0x80000001>,
|
||
|
|
<&dmamux1 14 0x400 0x80000001>,
|
||
|
|
<&dmamux1 15 0x400 0x80000001>,
|
||
|
|
<&dmamux1 16 0x400 0x80000001>,
|
||
|
|
<&dmamux1 17 0x400 0x80000001>;
|
||
|
|
dma-names = "ch1", "ch2", "ch3", "ch4",
|
||
|
|
"up", "trig", "com";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@0 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
counter {
|
||
|
|
compatible = "st,stm32-timer-counter";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timers8: timer@44001000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x44001000 0x400>;
|
||
|
|
clocks = <&rcc TIM8_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
dmas = <&dmamux1 47 0x400 0x80000001>,
|
||
|
|
<&dmamux1 48 0x400 0x80000001>,
|
||
|
|
<&dmamux1 49 0x400 0x80000001>,
|
||
|
|
<&dmamux1 50 0x400 0x80000001>,
|
||
|
|
<&dmamux1 51 0x400 0x80000001>,
|
||
|
|
<&dmamux1 52 0x400 0x80000001>,
|
||
|
|
<&dmamux1 53 0x400 0x80000001>;
|
||
|
|
dma-names = "ch1", "ch2", "ch3", "ch4",
|
||
|
|
"up", "trig", "com";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@7 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <7>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
counter {
|
||
|
|
compatible = "st,stm32-timer-counter";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
usart6: serial@44003000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x44003000 0x400>;
|
||
|
|
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc USART6_K>;
|
||
|
|
resets = <&rcc USART6_R>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
dmas = <&dmamux1 71 0x400 0x5>,
|
||
|
|
<&dmamux1 72 0x400 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi1: spi@44004000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x44004000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI1_K>;
|
||
|
|
resets = <&rcc SPI1_R>;
|
||
|
|
dmas = <&dmamux1 37 0x400 0x01>,
|
||
|
|
<&dmamux1 38 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2s1: audio-controller@44004000 {
|
||
|
|
compatible = "st,stm32h7-i2s";
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
reg = <0x44004000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 37 0x400 0x01>,
|
||
|
|
<&dmamux1 38 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi4: spi@44005000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x44005000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI4_K>;
|
||
|
|
resets = <&rcc SPI4_R>;
|
||
|
|
dmas = <&dmamux1 83 0x400 0x01>,
|
||
|
|
<&dmamux1 84 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timers15: timer@44006000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x44006000 0x400>;
|
||
|
|
clocks = <&rcc TIM15_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
dmas = <&dmamux1 105 0x400 0x80000001>,
|
||
|
|
<&dmamux1 106 0x400 0x80000001>,
|
||
|
|
<&dmamux1 107 0x400 0x80000001>,
|
||
|
|
<&dmamux1 108 0x400 0x80000001>;
|
||
|
|
dma-names = "ch1", "up", "trig", "com";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@14 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <14>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timers16: timer@44007000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x44007000 0x400>;
|
||
|
|
clocks = <&rcc TIM16_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
dmas = <&dmamux1 109 0x400 0x80000001>,
|
||
|
|
<&dmamux1 110 0x400 0x80000001>;
|
||
|
|
dma-names = "ch1", "up";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
timer@15 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <15>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timers17: timer@44008000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-timers";
|
||
|
|
reg = <0x44008000 0x400>;
|
||
|
|
clocks = <&rcc TIM17_K>;
|
||
|
|
clock-names = "int";
|
||
|
|
dmas = <&dmamux1 111 0x400 0x80000001>,
|
||
|
|
<&dmamux1 112 0x400 0x80000001>;
|
||
|
|
dma-names = "ch1", "up";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
timer@16 {
|
||
|
|
compatible = "st,stm32h7-timer-trigger";
|
||
|
|
reg = <16>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
spi5: spi@44009000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x44009000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc SPI5_K>;
|
||
|
|
resets = <&rcc SPI5_R>;
|
||
|
|
dmas = <&dmamux1 85 0x400 0x01>,
|
||
|
|
<&dmamux1 86 0x400 0x01>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sai1: sai@4400a000 {
|
||
|
|
compatible = "st,stm32h7-sai";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x4400a000 0x400>;
|
||
|
|
reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
|
||
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
resets = <&rcc SAI1_R>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
sai1a: audio-controller@4400a004 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
|
||
|
|
compatible = "st,stm32-sai-sub-a";
|
||
|
|
reg = <0x4 0x1c>;
|
||
|
|
clocks = <&rcc SAI1_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 87 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sai1b: audio-controller@4400a024 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-b";
|
||
|
|
reg = <0x24 0x1c>;
|
||
|
|
clocks = <&rcc SAI1_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 88 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sai2: sai@4400b000 {
|
||
|
|
compatible = "st,stm32h7-sai";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x4400b000 0x400>;
|
||
|
|
reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
|
||
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
resets = <&rcc SAI2_R>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
sai2a: audio-controller@4400b004 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-a";
|
||
|
|
reg = <0x4 0x1c>;
|
||
|
|
clocks = <&rcc SAI2_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 89 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sai2b: audio-controller@4400b024 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-b";
|
||
|
|
reg = <0x24 0x1c>;
|
||
|
|
clocks = <&rcc SAI2_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 90 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sai3: sai@4400c000 {
|
||
|
|
compatible = "st,stm32h7-sai";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x4400c000 0x400>;
|
||
|
|
reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
|
||
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
resets = <&rcc SAI3_R>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
sai3a: audio-controller@4400c004 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-a";
|
||
|
|
reg = <0x04 0x1c>;
|
||
|
|
clocks = <&rcc SAI3_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 113 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sai3b: audio-controller@4400c024 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-b";
|
||
|
|
reg = <0x24 0x1c>;
|
||
|
|
clocks = <&rcc SAI3_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 114 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
dfsdm: dfsdm@4400d000 {
|
||
|
|
compatible = "st,stm32mp1-dfsdm";
|
||
|
|
reg = <0x4400d000 0x800>;
|
||
|
|
clocks = <&rcc DFSDM_K>;
|
||
|
|
clock-names = "dfsdm";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
dfsdm0: filter@0 {
|
||
|
|
compatible = "st,stm32-dfsdm-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <0>;
|
||
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 101 0x400 0x01>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dfsdm1: filter@1 {
|
||
|
|
compatible = "st,stm32-dfsdm-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <1>;
|
||
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 102 0x400 0x01>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dfsdm2: filter@2 {
|
||
|
|
compatible = "st,stm32-dfsdm-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <2>;
|
||
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 103 0x400 0x01>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dfsdm3: filter@3 {
|
||
|
|
compatible = "st,stm32-dfsdm-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <3>;
|
||
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 104 0x400 0x01>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dfsdm4: filter@4 {
|
||
|
|
compatible = "st,stm32-dfsdm-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <4>;
|
||
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 91 0x400 0x01>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dfsdm5: filter@5 {
|
||
|
|
compatible = "st,stm32-dfsdm-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <5>;
|
||
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&dmamux1 92 0x400 0x01>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
dma1: dma@48000000 {
|
||
|
|
compatible = "st,stm32-dma";
|
||
|
|
reg = <0x48000000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc DMA1>;
|
||
|
|
resets = <&rcc DMA1_R>;
|
||
|
|
#dma-cells = <4>;
|
||
|
|
st,mem2mem;
|
||
|
|
dma-requests = <8>;
|
||
|
|
dmas = <&mdma1 0 0x3 0x1200000a 0x48000008 0x00000020 1>,
|
||
|
|
<&mdma1 1 0x3 0x1200000a 0x48000008 0x00000800 1>,
|
||
|
|
<&mdma1 2 0x3 0x1200000a 0x48000008 0x00200000 1>,
|
||
|
|
<&mdma1 3 0x3 0x1200000a 0x48000008 0x08000000 1>,
|
||
|
|
<&mdma1 4 0x3 0x1200000a 0x4800000C 0x00000020 1>,
|
||
|
|
<&mdma1 5 0x3 0x1200000a 0x4800000C 0x00000800 1>,
|
||
|
|
<&mdma1 6 0x3 0x1200000a 0x4800000C 0x00200000 1>,
|
||
|
|
<&mdma1 7 0x3 0x1200000a 0x4800000C 0x08000000 1>;
|
||
|
|
dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
||
|
|
};
|
||
|
|
|
||
|
|
dma2: dma@48001000 {
|
||
|
|
compatible = "st,stm32-dma";
|
||
|
|
reg = <0x48001000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc DMA2>;
|
||
|
|
resets = <&rcc DMA2_R>;
|
||
|
|
#dma-cells = <4>;
|
||
|
|
st,mem2mem;
|
||
|
|
dma-requests = <8>;
|
||
|
|
dmas = <&mdma1 8 0x3 0x1200000a 0x48001008 0x00000020 1>,
|
||
|
|
<&mdma1 9 0x3 0x1200000a 0x48001008 0x00000800 1>,
|
||
|
|
<&mdma1 10 0x3 0x1200000a 0x48001008 0x00200000 1>,
|
||
|
|
<&mdma1 11 0x3 0x1200000a 0x48001008 0x08000000 1>,
|
||
|
|
<&mdma1 12 0x3 0x1200000a 0x4800100C 0x00000020 1>,
|
||
|
|
<&mdma1 13 0x3 0x1200000a 0x4800100C 0x00000800 1>,
|
||
|
|
<&mdma1 14 0x3 0x1200000a 0x4800100C 0x00200000 1>,
|
||
|
|
<&mdma1 15 0x3 0x1200000a 0x4800100C 0x08000000 1>;
|
||
|
|
dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
||
|
|
};
|
||
|
|
|
||
|
|
dmamux1: dma-router@48002000 {
|
||
|
|
compatible = "st,stm32h7-dmamux";
|
||
|
|
reg = <0x48002000 0x40>;
|
||
|
|
#dma-cells = <3>;
|
||
|
|
dma-requests = <128>;
|
||
|
|
dma-masters = <&dma1 &dma2>;
|
||
|
|
dma-channels = <16>;
|
||
|
|
clocks = <&rcc DMAMUX>;
|
||
|
|
resets = <&rcc DMAMUX_R>;
|
||
|
|
};
|
||
|
|
|
||
|
|
adc: adc@48003000 {
|
||
|
|
compatible = "st,stm32mp1-adc-core";
|
||
|
|
reg = <0x48003000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
||
|
|
clock-names = "bus", "adc";
|
||
|
|
interrupt-controller;
|
||
|
|
st,syscfg = <&syscfg>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
adc1: adc@0 {
|
||
|
|
compatible = "st,stm32mp1-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <0x0>;
|
||
|
|
interrupt-parent = <&adc>;
|
||
|
|
interrupts = <0>;
|
||
|
|
dmas = <&dmamux1 9 0x400 0x80000001>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
adc2: adc@100 {
|
||
|
|
compatible = "st,stm32mp1-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <0x100>;
|
||
|
|
interrupt-parent = <&adc>;
|
||
|
|
interrupts = <1>;
|
||
|
|
dmas = <&dmamux1 10 0x400 0x80000001>;
|
||
|
|
dma-names = "rx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdmmc3: sdmmc@48004000 {
|
||
|
|
compatible = "arm,pl18x", "arm,primecell";
|
||
|
|
arm,primecell-periphid = <0x00253180>;
|
||
|
|
reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "cmd_irq";
|
||
|
|
clocks = <&rcc SDMMC3_K>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
resets = <&rcc SDMMC3_R>;
|
||
|
|
cap-sd-highspeed;
|
||
|
|
cap-mmc-highspeed;
|
||
|
|
max-frequency = <120000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usbotg_hs: usb-otg@49000000 {
|
||
|
|
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
||
|
|
reg = <0x49000000 0x10000>;
|
||
|
|
clocks = <&rcc USBO_K>;
|
||
|
|
clock-names = "otg";
|
||
|
|
resets = <&rcc USBO_R>;
|
||
|
|
reset-names = "dwc2";
|
||
|
|
interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
g-rx-fifo-size = <512>;
|
||
|
|
g-np-tx-fifo-size = <32>;
|
||
|
|
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
|
||
|
|
dr_mode = "otg";
|
||
|
|
usb33d-supply = <&usb33>;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
hsem: hwspinlock@4c000000 {
|
||
|
|
compatible = "st,stm32-hwspinlock";
|
||
|
|
#hwlock-cells = <2>;
|
||
|
|
reg = <0x4c000000 0x400>;
|
||
|
|
clocks = <&rcc HSEM>;
|
||
|
|
clock-names = "hsem";
|
||
|
|
};
|
||
|
|
|
||
|
|
ipcc: mailbox@4c001000 {
|
||
|
|
compatible = "st,stm32mp1-ipcc";
|
||
|
|
#mbox-cells = <1>;
|
||
|
|
reg = <0x4c001000 0x400>;
|
||
|
|
st,proc-id = <0>;
|
||
|
|
interrupts-extended =
|
||
|
|
<&exti 61 1>,
|
||
|
|
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "rx", "tx";
|
||
|
|
clocks = <&rcc IPCC>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dcmi: dcmi@4c006000 {
|
||
|
|
compatible = "st,stm32-dcmi";
|
||
|
|
reg = <0x4c006000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
resets = <&rcc CAMITF_R>;
|
||
|
|
clocks = <&rcc DCMI>;
|
||
|
|
clock-names = "mclk";
|
||
|
|
dmas = <&dmamux1 75 0x400 0xe0000001>;
|
||
|
|
dma-names = "tx";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rcc: rcc@50000000 {
|
||
|
|
compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
|
||
|
|
reg = <0x50000000 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_HSE>,
|
||
|
|
<&scmi0_clk CK_SCMI0_HSI>,
|
||
|
|
<&scmi0_clk CK_SCMI0_CSI>,
|
||
|
|
<&scmi0_clk CK_SCMI0_LSE>,
|
||
|
|
<&scmi0_clk CK_SCMI0_LSI>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pwr_regulators: pwr@50001000 {
|
||
|
|
compatible = "st,stm32mp1,pwr-reg";
|
||
|
|
reg = <0x50001000 0x10>;
|
||
|
|
st,tzcr = <&rcc 0x0 0x1>;
|
||
|
|
|
||
|
|
reg11: reg11 {
|
||
|
|
regulator-name = "reg11";
|
||
|
|
regulator-min-microvolt = <1100000>;
|
||
|
|
regulator-max-microvolt = <1100000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
reg18: reg18 {
|
||
|
|
regulator-name = "reg18";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usb33: usb33 {
|
||
|
|
regulator-name = "usb33";
|
||
|
|
regulator-min-microvolt = <3300000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pwr_mcu: pwr_mcu@50001014 {
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0x50001014 0x4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pwr_irq: pwr@50001020 {
|
||
|
|
compatible = "st,stm32mp1-pwr";
|
||
|
|
reg = <0x50001020 0x100>;
|
||
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
|
||
|
|
wakeup-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>,
|
||
|
|
<&gpioa 2 GPIO_ACTIVE_HIGH>,
|
||
|
|
<&gpioc 13 GPIO_ACTIVE_HIGH>,
|
||
|
|
<&gpioi 8 GPIO_ACTIVE_HIGH>,
|
||
|
|
<&gpioi 11 GPIO_ACTIVE_HIGH>,
|
||
|
|
<&gpioc 1 GPIO_ACTIVE_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
exti: interrupt-controller@5000d000 {
|
||
|
|
compatible = "st,stm32mp1-exti", "syscon";
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x5000d000 0x400>;
|
||
|
|
hwlocks = <&hsem 1 1>;
|
||
|
|
|
||
|
|
/* exti_pwr is an extra interrupt controller used for
|
||
|
|
* EXTI 55 to 60. It's mapped on pwr interrupt
|
||
|
|
* controller.
|
||
|
|
*/
|
||
|
|
exti_pwr: exti-pwr {
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-parent = <&pwr_irq>;
|
||
|
|
st,irq-number = <6>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
syscfg: syscon@50020000 {
|
||
|
|
compatible = "st,stm32mp157-syscfg", "syscon";
|
||
|
|
reg = <0x50020000 0x400>;
|
||
|
|
clocks = <&rcc SYSCFG>;
|
||
|
|
};
|
||
|
|
|
||
|
|
lptimer2: timer@50021000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-lptimer";
|
||
|
|
reg = <0x50021000 0x400>;
|
||
|
|
clocks = <&rcc LPTIM2_K>;
|
||
|
|
clock-names = "mux";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm-lp";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
trigger@1 {
|
||
|
|
compatible = "st,stm32-lptimer-trigger";
|
||
|
|
reg = <1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
counter {
|
||
|
|
compatible = "st,stm32-lptimer-counter";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
lptimer3: timer@50022000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32-lptimer";
|
||
|
|
reg = <0x50022000 0x400>;
|
||
|
|
clocks = <&rcc LPTIM3_K>;
|
||
|
|
clock-names = "mux";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm-lp";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
trigger@2 {
|
||
|
|
compatible = "st,stm32-lptimer-trigger";
|
||
|
|
reg = <2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
lptimer4: timer@50023000 {
|
||
|
|
compatible = "st,stm32-lptimer";
|
||
|
|
reg = <0x50023000 0x400>;
|
||
|
|
clocks = <&rcc LPTIM4_K>;
|
||
|
|
clock-names = "mux";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm-lp";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
lptimer5: timer@50024000 {
|
||
|
|
compatible = "st,stm32-lptimer";
|
||
|
|
reg = <0x50024000 0x400>;
|
||
|
|
clocks = <&rcc LPTIM5_K>;
|
||
|
|
clock-names = "mux";
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
pwm {
|
||
|
|
compatible = "st,stm32-pwm-lp";
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
vrefbuf: vrefbuf@50025000 {
|
||
|
|
compatible = "st,stm32-vrefbuf";
|
||
|
|
reg = <0x50025000 0x8>;
|
||
|
|
regulator-min-microvolt = <1500000>;
|
||
|
|
regulator-max-microvolt = <2500000>;
|
||
|
|
clocks = <&rcc VREF>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sai4: sai@50027000 {
|
||
|
|
compatible = "st,stm32h7-sai";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
ranges = <0 0x50027000 0x400>;
|
||
|
|
reg = <0x50027000 0x4>, <0x500273f0 0x10>;
|
||
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
resets = <&rcc SAI4_R>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
sai4a: audio-controller@50027004 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-a";
|
||
|
|
reg = <0x04 0x1c>;
|
||
|
|
clocks = <&rcc SAI4_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 99 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sai4b: audio-controller@50027024 {
|
||
|
|
#sound-dai-cells = <0>;
|
||
|
|
compatible = "st,stm32-sai-sub-b";
|
||
|
|
reg = <0x24 0x1c>;
|
||
|
|
clocks = <&rcc SAI4_K>;
|
||
|
|
clock-names = "sai_ck";
|
||
|
|
dmas = <&dmamux1 100 0x400 0x01>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
dts: thermal@50028000 {
|
||
|
|
compatible = "st,stm32-thermal";
|
||
|
|
reg = <0x50028000 0x100>;
|
||
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc TMPSENS>;
|
||
|
|
clock-names = "pclk";
|
||
|
|
#thermal-sensor-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
hdp: hdp@5002a000 {
|
||
|
|
compatible = "st,stm32mp1-hdp";
|
||
|
|
reg = <0x5002a000 0x400>;
|
||
|
|
clocks = <&rcc HDP>;
|
||
|
|
clock-names = "hdp";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
hash1: hash@54002000 {
|
||
|
|
compatible = "st,stm32f756-hash";
|
||
|
|
reg = <0x54002000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_HASH1>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_HASH1>;
|
||
|
|
dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0 0x0>;
|
||
|
|
dma-names = "in";
|
||
|
|
dma-maxburst = <2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rng1: rng@54003000 {
|
||
|
|
compatible = "st,stm32-rng";
|
||
|
|
reg = <0x54003000 0x400>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_RNG1>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_RNG1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
mdma1: dma@58000000 {
|
||
|
|
compatible = "st,stm32h7-mdma";
|
||
|
|
reg = <0x58000000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc MDMA>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_MDMA>;
|
||
|
|
#dma-cells = <6>;
|
||
|
|
dma-channels = <32>;
|
||
|
|
dma-requests = <48>;
|
||
|
|
};
|
||
|
|
|
||
|
|
fmc: nand-controller@58002000 {
|
||
|
|
compatible = "st,stm32mp15-fmc2";
|
||
|
|
reg = <0x58002000 0x1000>,
|
||
|
|
<0x80000000 0x1000>,
|
||
|
|
<0x88010000 0x1000>,
|
||
|
|
<0x88020000 0x1000>,
|
||
|
|
<0x81000000 0x1000>,
|
||
|
|
<0x89010000 0x1000>,
|
||
|
|
<0x89020000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0 0x0>,
|
||
|
|
<&mdma1 20 0x2 0x12000a08 0x0 0x0 0x0>,
|
||
|
|
<&mdma1 21 0x2 0x12000a0a 0x0 0x0 0x0>;
|
||
|
|
dma-names = "tx", "rx", "ecc";
|
||
|
|
clocks = <&rcc FMC_K>;
|
||
|
|
resets = <&rcc FMC_R>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
qspi: spi@58003000 {
|
||
|
|
compatible = "st,stm32f469-qspi";
|
||
|
|
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||
|
|
reg-names = "qspi", "qspi_mm";
|
||
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
dmas = <&mdma1 22 0x2 0x100002 0x0 0x0 0x0>,
|
||
|
|
<&mdma1 22 0x2 0x100008 0x0 0x0 0x0>;
|
||
|
|
dma-names = "tx", "rx";
|
||
|
|
clocks = <&rcc QSPI_K>;
|
||
|
|
resets = <&rcc QSPI_R>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdmmc1: sdmmc@58005000 {
|
||
|
|
compatible = "arm,pl18x", "arm,primecell";
|
||
|
|
arm,primecell-periphid = <0x00253180>;
|
||
|
|
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "cmd_irq";
|
||
|
|
clocks = <&rcc SDMMC1_K>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
resets = <&rcc SDMMC1_R>;
|
||
|
|
cap-sd-highspeed;
|
||
|
|
cap-mmc-highspeed;
|
||
|
|
max-frequency = <120000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdmmc2: sdmmc@58007000 {
|
||
|
|
compatible = "arm,pl18x", "arm,primecell";
|
||
|
|
arm,primecell-periphid = <0x00253180>;
|
||
|
|
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "cmd_irq";
|
||
|
|
clocks = <&rcc SDMMC2_K>;
|
||
|
|
clock-names = "apb_pclk";
|
||
|
|
resets = <&rcc SDMMC2_R>;
|
||
|
|
cap-sd-highspeed;
|
||
|
|
cap-mmc-highspeed;
|
||
|
|
max-frequency = <120000000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
crc1: crc@58009000 {
|
||
|
|
compatible = "st,stm32f7-crc";
|
||
|
|
reg = <0x58009000 0x400>;
|
||
|
|
clocks = <&rcc CRC1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
stmmac_axi_config_0: stmmac-axi-config {
|
||
|
|
snps,wr_osr_lmt = <0x7>;
|
||
|
|
snps,rd_osr_lmt = <0x7>;
|
||
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ethernet0: ethernet@5800a000 {
|
||
|
|
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
|
||
|
|
reg = <0x5800a000 0x2000>;
|
||
|
|
reg-names = "stmmaceth";
|
||
|
|
interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&exti 70 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "macirq",
|
||
|
|
"eth_wake_irq";
|
||
|
|
clock-names = "stmmaceth",
|
||
|
|
"mac-clk-tx",
|
||
|
|
"mac-clk-rx",
|
||
|
|
"ethstp";
|
||
|
|
clocks = <&rcc ETHMAC>,
|
||
|
|
<&rcc ETHTX>,
|
||
|
|
<&rcc ETHRX>,
|
||
|
|
<&rcc ETHSTP>;
|
||
|
|
st,syscon = <&syscfg 0x4>;
|
||
|
|
snps,mixed-burst;
|
||
|
|
snps,pbl = <2>;
|
||
|
|
snps,en-tx-lpi-clockgating;
|
||
|
|
snps,axi-config = <&stmmac_axi_config_0>;
|
||
|
|
snps,tso;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usbh_ohci: usbh-ohci@5800c000 {
|
||
|
|
compatible = "generic-ohci";
|
||
|
|
reg = <0x5800c000 0x1000>;
|
||
|
|
clocks = <&rcc USBH>;
|
||
|
|
resets = <&rcc USBH_R>;
|
||
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usbh_ehci: usbh-ehci@5800d000 {
|
||
|
|
compatible = "generic-ehci";
|
||
|
|
reg = <0x5800d000 0x1000>;
|
||
|
|
clocks = <&rcc USBH>;
|
||
|
|
resets = <&rcc USBH_R>;
|
||
|
|
interrupts-extended = <&exti 43 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
companion = <&usbh_ohci>;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
ltdc: display-controller@5a001000 {
|
||
|
|
compatible = "st,stm32-ltdc";
|
||
|
|
reg = <0x5a001000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc LTDC_PX>;
|
||
|
|
clock-names = "lcd";
|
||
|
|
resets = <&rcc LTDC_R>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
iwdg2: watchdog@5a002000 {
|
||
|
|
compatible = "st,stm32mp1-iwdg";
|
||
|
|
reg = <0x5a002000 0x400>;
|
||
|
|
clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>;
|
||
|
|
clock-names = "pclk", "lsi";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
usbphyc: usbphyc@5a006000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "st,stm32mp1-usbphyc";
|
||
|
|
reg = <0x5a006000 0x1000>;
|
||
|
|
clocks = <&rcc USBPHY_K>;
|
||
|
|
resets = <&rcc USBPHY_R>;
|
||
|
|
vdda1v1-supply = <®11>;
|
||
|
|
vdda1v8-supply = <®18>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
usbphyc_port0: usb-phy@0 {
|
||
|
|
#phy-cells = <0>;
|
||
|
|
reg = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usbphyc_port1: usb-phy@1 {
|
||
|
|
#phy-cells = <1>;
|
||
|
|
reg = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
ddrperfm: perf@5a007000 {
|
||
|
|
compatible = "st,stm32-ddr-pmu";
|
||
|
|
reg = <0x5a007000 0x400>;
|
||
|
|
clocks = <&rcc DDRPERFM>, <&scmi0_clk CK_SCMI0_PLL2_R>;
|
||
|
|
clock-names = "bus", "ddr";
|
||
|
|
resets = <&rcc DDRPERFM_R>;
|
||
|
|
};
|
||
|
|
|
||
|
|
usart1: serial@5c000000 {
|
||
|
|
compatible = "st,stm32h7-uart";
|
||
|
|
reg = <0x5c000000 0x400>;
|
||
|
|
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_USART1>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_USART1>;
|
||
|
|
wakeup-source;
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi6: spi@5c001000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "st,stm32h7-spi";
|
||
|
|
reg = <0x5c001000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_SPI6>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_SPI6>;
|
||
|
|
dmas = <&mdma1 34 0x0 0x40008 0x0 0x0 0x0>,
|
||
|
|
<&mdma1 35 0x0 0x40002 0x0 0x0 0x0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c4: i2c@5c002000 {
|
||
|
|
compatible = "st,stm32mp15-i2c";
|
||
|
|
reg = <0x5c002000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_I2C4>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_I2C4>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&mdma1 36 0x0 0x40008 0x0 0x0 0>,
|
||
|
|
<&mdma1 37 0x0 0x40002 0x0 0x0 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x8>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rtc: rtc@5c004000 {
|
||
|
|
compatible = "st,stm32mp1-rtc";
|
||
|
|
reg = <0x5c004000 0x400>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_RTCAPB>,
|
||
|
|
<&scmi0_clk CK_SCMI0_RTC>;
|
||
|
|
clock-names = "pclk", "rtc_ck";
|
||
|
|
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
bsec: nvmem@5c005000 {
|
||
|
|
compatible = "st,stm32mp15-bsec";
|
||
|
|
reg = <0x5c005000 0x400>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
|
||
|
|
part_number_otp: part_number_otp@4 {
|
||
|
|
reg = <0x4 0x1>;
|
||
|
|
};
|
||
|
|
ts_cal1: calib@5c {
|
||
|
|
reg = <0x5c 0x2>;
|
||
|
|
};
|
||
|
|
ts_cal2: calib@5e {
|
||
|
|
reg = <0x5e 0x2>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c6: i2c@5c009000 {
|
||
|
|
compatible = "st,stm32mp15-i2c";
|
||
|
|
reg = <0x5c009000 0x400>;
|
||
|
|
interrupt-names = "event", "error";
|
||
|
|
interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_I2C6>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_I2C6>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
dmas = <&mdma1 38 0x0 0x40008 0x0 0x0 0>,
|
||
|
|
<&mdma1 39 0x0 0x40002 0x0 0x0 0>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
power-domains = <&pd_core>;
|
||
|
|
st,syscfg-fmp = <&syscfg 0x4 0x20>;
|
||
|
|
wakeup-source;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
tamp: tamp@5c00a000 {
|
||
|
|
compatible = "simple-bus", "syscon", "simple-mfd";
|
||
|
|
reg = <0x5c00a000 0x400>;
|
||
|
|
|
||
|
|
reboot-mode {
|
||
|
|
compatible = "syscon-reboot-mode";
|
||
|
|
offset = <0x150>; /* reg20 */
|
||
|
|
mask = <0xff>;
|
||
|
|
mode-normal = <0>;
|
||
|
|
mode-fastboot = <0x1>;
|
||
|
|
mode-recovery = <0x2>;
|
||
|
|
mode-stm32cubeprogrammer = <0x3>;
|
||
|
|
mode-ums_mmc0 = <0x10>;
|
||
|
|
mode-ums_mmc1 = <0x11>;
|
||
|
|
mode-ums_mmc2 = <0x12>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Break node order to solve dependency probe issue between
|
||
|
|
* pinctrl and exti.
|
||
|
|
*/
|
||
|
|
pinctrl: pin-controller@50002000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stm32mp157-pinctrl";
|
||
|
|
ranges = <0 0x50002000 0xa400>;
|
||
|
|
interrupt-parent = <&exti>;
|
||
|
|
st,syscfg = <&exti 0x60 0xff>;
|
||
|
|
hwlocks = <&hsem 0 1>;
|
||
|
|
pins-are-numbered;
|
||
|
|
|
||
|
|
gpioa: gpio@50002000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x0 0x400>;
|
||
|
|
clocks = <&rcc GPIOA>;
|
||
|
|
st,bank-name = "GPIOA";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiob: gpio@50003000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x400>;
|
||
|
|
clocks = <&rcc GPIOB>;
|
||
|
|
st,bank-name = "GPIOB";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioc: gpio@50004000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x400>;
|
||
|
|
clocks = <&rcc GPIOC>;
|
||
|
|
st,bank-name = "GPIOC";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiod: gpio@50005000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x3000 0x400>;
|
||
|
|
clocks = <&rcc GPIOD>;
|
||
|
|
st,bank-name = "GPIOD";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioe: gpio@50006000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x4000 0x400>;
|
||
|
|
clocks = <&rcc GPIOE>;
|
||
|
|
st,bank-name = "GPIOE";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiof: gpio@50007000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x5000 0x400>;
|
||
|
|
clocks = <&rcc GPIOF>;
|
||
|
|
st,bank-name = "GPIOF";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiog: gpio@50008000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x6000 0x400>;
|
||
|
|
clocks = <&rcc GPIOG>;
|
||
|
|
st,bank-name = "GPIOG";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioh: gpio@50009000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x7000 0x400>;
|
||
|
|
clocks = <&rcc GPIOH>;
|
||
|
|
st,bank-name = "GPIOH";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioi: gpio@5000a000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x8000 0x400>;
|
||
|
|
clocks = <&rcc GPIOI>;
|
||
|
|
st,bank-name = "GPIOI";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpioj: gpio@5000b000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x9000 0x400>;
|
||
|
|
clocks = <&rcc GPIOJ>;
|
||
|
|
st,bank-name = "GPIOJ";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
gpiok: gpio@5000c000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0xa000 0x400>;
|
||
|
|
clocks = <&rcc GPIOK>;
|
||
|
|
st,bank-name = "GPIOK";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_z: pin-controller-z@54004000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stm32mp157-z-pinctrl";
|
||
|
|
ranges = <0 0x54004000 0x400>;
|
||
|
|
pins-are-numbered;
|
||
|
|
interrupt-parent = <&exti>;
|
||
|
|
st,syscfg = <&exti 0x60 0xff>;
|
||
|
|
hwlocks = <&hsem 0 1>;
|
||
|
|
|
||
|
|
gpioz: gpio@54004000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0 0x400>;
|
||
|
|
clocks = <&scmi0_clk CK_SCMI0_GPIOZ>;
|
||
|
|
st,bank-name = "GPIOZ";
|
||
|
|
st,bank-ioport = <11>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mlahb {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
dma-ranges = <0x00000000 0x38000000 0x10000>,
|
||
|
|
<0x10000000 0x10000000 0x60000>,
|
||
|
|
<0x30000000 0x30000000 0x60000>;
|
||
|
|
|
||
|
|
m4_rproc: m4@10000000 {
|
||
|
|
compatible = "st,stm32mp1-m4";
|
||
|
|
reg = <0x10000000 0x40000>,
|
||
|
|
<0x30000000 0x40000>,
|
||
|
|
<0x38000000 0x10000>;
|
||
|
|
resets = <&scmi0_reset RST_SCMI0_MCU>;
|
||
|
|
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
|
||
|
|
st,syscfg-tz = <&rcc 0x000 0x1>;
|
||
|
|
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
|
||
|
|
st,syscfg-copro-state = <&tamp 0x148 0xFFFFFFFF>;
|
||
|
|
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
|
||
|
|
status = "disabled";
|
||
|
|
|
||
|
|
m4_system_resources {
|
||
|
|
compatible = "rproc-srm-core";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|