85 lines
1.5 KiB
Plaintext
85 lines
1.5 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright(c) 2015 EZchip Technologies.
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*/
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/dts-v1/;
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/ {
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compatible = "ezchip,arc-nps";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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present-cpus = "0-1,16-17";
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possible-cpus = "0-4095";
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aliases {
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ethernet0 = &gmac0;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8 console=ttyS0,115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512M */
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};
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clocks {
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <83333333>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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intc: interrupt-controller {
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compatible = "ezchip,nps400-ic";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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timer0: timer_clkevt {
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compatible = "snps,arc-timer";
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interrupts = <3>;
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clocks = <&sysclk>;
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};
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timer1: timer_clksrc {
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compatible = "ezchip,nps400-timer";
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clocks = <&sysclk>;
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clock-names="sysclk";
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};
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uart@f7209000 {
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compatible = "snps,dw-apb-uart";
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device_type = "serial";
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reg = <0xf7209000 0x100>;
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interrupts = <6>;
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clocks = <&sysclk>;
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clock-names="baudclk";
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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native-endian;
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};
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gmac0: ethernet@f7470000 {
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compatible = "ezchip,nps-mgt-enet";
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reg = <0xf7470000 0x1940>;
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interrupts = <7>;
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/* Filled in by U-Boot */
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mac-address = [ 00 C0 00 F0 04 03 ];
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};
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};
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};
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