32 lines
987 B
Plaintext
32 lines
987 B
Plaintext
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LogicoreIP designed compatible with Xilinx ZYNQ family.
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-------------------------------------------------------
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General concept
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---------------
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LogicoreIP design to provide the isolation between processing system
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and programmable logic. Also provides the list of register set to configure
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the frequency.
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Required properties:
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- compatible: shall be one of:
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"xlnx,vcu"
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"xlnx,vcu-logicoreip-1.0"
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- reg, reg-names: There are two sets of registers need to provide.
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1. vcu slcr
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2. Logicore
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reg-names should contain name for the each register sequence.
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- clocks: phandle for aclk and pll_ref clocksource
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- clock-names: The identification string, "aclk", is always required for
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the axi clock. "pll_ref" is required for pll.
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Example:
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xlnx_vcu: vcu@a0040000 {
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compatible = "xlnx,vcu-logicoreip-1.0";
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reg = <0x0 0xa0040000 0x0 0x1000>,
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<0x0 0xa0041000 0x0 0x1000>;
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reg-names = "vcu_slcr", "logicore";
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clocks = <&si570_1>, <&clkc 71>;
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clock-names = "pll_ref", "aclk";
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};
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