28 lines
985 B
Plaintext
28 lines
985 B
Plaintext
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Binding for Cadence UART Controller
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Required properties:
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- compatible :
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Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
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Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
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- reg: Should contain UART controller registers location and length.
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- interrupts: Should contain UART controller interrupts.
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- clocks: Must contain phandles to the UART clocks
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
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See ../clocks/clock-bindings.txt for details.
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Optional properties:
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- cts-override : Override the CTS modem status signal. This signal will
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always be reported as active instead of being obtained from the modem status
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register. Define this if your serial port does not use this pin
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Example:
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uart@e0000000 {
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compatible = "cdns,uart-r1p8";
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clocks = <&clkc 23>, <&clkc 40>;
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clock-names = "uart_clk", "pclk";
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reg = <0xE0000000 0x1000>;
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interrupts = <0 27 4>;
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};
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