96 lines
3.3 KiB
Plaintext
96 lines
3.3 KiB
Plaintext
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* UART (Universal Asynchronous Receiver/Transmitter)
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Required properties:
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- compatible : one of:
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- "ns8250"
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- "ns16450"
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- "ns16550a"
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- "ns16550"
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- "ns16750"
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- "ns16850"
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- For Tegra20, must contain "nvidia,tegra20-uart"
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- For other Tegra, must contain '"nvidia,<chip>-uart",
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"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
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tegra132, or tegra210.
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- "nxp,lpc3220-uart"
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- "ralink,rt2880-uart"
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- For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
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"mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
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- "altr,16550-FIFO32"
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- "altr,16550-FIFO64"
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- "altr,16550-FIFO128"
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- "fsl,16550-FIFO64"
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- "fsl,ns16550"
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- "intel,xscale-uart"
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- "ti,da830-uart"
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- "aspeed,ast2400-vuart"
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- "aspeed,ast2500-vuart"
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- "nuvoton,npcm750-uart"
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- "serial" if the port type is unknown.
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- reg : offset and length of the register set for the device.
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- interrupts : should contain uart interrupt.
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- clock-frequency : the input clock frequency for the UART
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or
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clocks phandle to refer to the clk used as per Documentation/devicetree
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/bindings/clock/clock-bindings.txt
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Optional properties:
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- current-speed : the current active speed of the UART.
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- reg-offset : offset to apply to the mapbase from the start of the registers.
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- reg-shift : quantity to shift the register offsets by.
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- reg-io-width : the size (in bytes) of the IO accesses that should be
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performed on the device. There are some systems that require 32-bit
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accesses to the UART (e.g. TI davinci).
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- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
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RTAS and should not be registered.
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- no-loopback-test: set to indicate that the port does not implements loopback
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test mode
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- fifo-size: the fifo size of the UART.
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- auto-flow-control: one way to enable automatic flow control support. The
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driver is allowed to detect support for the capability even without this
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property.
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- tx-threshold: Specify the TX FIFO low water indication for parts with
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programmable TX FIFO thresholds.
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- resets : phandle + reset specifier pairs
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- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered.
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- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
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line respectively. It will use specified GPIO instead of the peripheral
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function pin for the UART feature. If unsure, don't specify this property.
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Note:
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* fsl,ns16550:
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------------
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Freescale DUART is very similar to the PC16552D (and to a
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pair of NS16550A), albeit with some nonstandard behavior such as
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erratum A-004737 (relating to incorrect BRK handling).
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Represents a single port that is compatible with the DUART found
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on many Freescale chips (examples include mpc8349, mpc8548,
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mpc8641d, p4080 and ls2085a).
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Example:
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uart@80230000 {
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compatible = "ns8250";
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reg = <0x80230000 0x100>;
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clock-frequency = <3686400>;
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interrupts = <10>;
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reg-shift = <2>;
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};
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Example for OMAP UART using GPIO-based modem control signals:
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uart4: serial@49042000 {
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compatible = "ti,omap3-uart";
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reg = <0x49042000 0x400>;
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interrupts = <80>;
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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