86 lines
3.3 KiB
Plaintext
86 lines
3.3 KiB
Plaintext
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* Freescale QorIQ 1588 timer based PTP clock
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General Properties:
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- compatible Should be "fsl,etsec-ptp" for eTSEC
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Should be "fsl,fman-ptp-timer" for DPAA FMan
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Should be "fsl,dpaa2-ptp" for DPAA2
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Should be "fsl,enetc-ptp" for ENETC
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- reg Offset and length of the register set for the device
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- interrupts There should be at least two interrupts. Some devices
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have as many as four PTP related interrupts.
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Clock Properties:
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- fsl,cksel Timer reference clock source.
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- fsl,tclk-period Timer reference clock period in nanoseconds.
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- fsl,tmr-prsc Prescaler, divides the output clock.
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- fsl,tmr-add Frequency compensation value.
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- fsl,tmr-fiper1 Fixed interval period pulse generator.
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- fsl,tmr-fiper2 Fixed interval period pulse generator.
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- fsl,max-adj Maximum frequency adjustment in parts per billion.
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- fsl,extts-fifo The presence of this property indicates hardware
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support for the external trigger stamp FIFO.
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- little-endian The presence of this property indicates the 1588 timer
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IP block is little-endian mode. The default endian mode
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is big-endian.
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These properties set the operational parameters for the PTP
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clock. You must choose these carefully for the clock to work right.
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Here is how to figure good values:
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TimerOsc = selected reference clock MHz
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tclk_period = desired clock period nanoseconds
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NominalFreq = 1000 / tclk_period MHz
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FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
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tmr_add = ceil(2^32 / FreqDivRatio)
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OutputClock = NominalFreq / tmr_prsc MHz
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PulseWidth = 1 / OutputClock microseconds
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FiperFreq1 = desired frequency in Hz
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FiperDiv1 = 1000000 * OutputClock / FiperFreq1
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tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
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max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
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The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
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driver expects that tmr_fiper1 will be correctly set to produce a 1
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Pulse Per Second (PPS) signal, since this will be offered to the PPS
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subsystem to synchronize the Linux clock.
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Reference clock source is determined by the value, which is holded
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in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
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value, which will be directly written in those bits, that is why,
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according to reference manual, the next clock sources can be used:
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For eTSEC,
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<0> - external high precision timer reference clock (TSEC_TMR_CLK
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input is used for this purpose);
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<1> - eTSEC system clock;
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<2> - eTSEC1 transmit clock;
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<3> - RTC clock input.
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For DPAA FMan,
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<0> - external high precision timer reference clock (TMR_1588_CLK)
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<1> - MAC system clock (1/2 FMan clock)
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<2> - reserved
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<3> - RTC clock oscillator
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When this attribute is not used, the IEEE 1588 timer reference clock
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will use the eTSEC system clock (for Gianfar) or the MAC system
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clock (for DPAA).
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Example:
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ptp_clock@24e00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <12 0x8 13 0x8>;
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interrupt-parent = < &ipic >;
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fsl,cksel = <1>;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <100>;
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fsl,tmr-add = <0x999999A4>;
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fsl,tmr-fiper1 = <0x3B9AC9F6>;
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fsl,tmr-fiper2 = <0x00018696>;
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fsl,max-adj = <659999998>;
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};
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