53 lines
1.8 KiB
Plaintext
53 lines
1.8 KiB
Plaintext
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PPC4xx Clock Power Management (CPM) node
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Required properties:
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- compatible : compatible list, currently only "ibm,cpm"
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- dcr-access-method : "native"
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- dcr-reg : < DCR register range >
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Optional properties:
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- er-offset : All 4xx SoCs with a CPM controller have
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one of two different order for the CPM
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registers. Some have the CPM registers
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in the following order (ER,FR,SR). The
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others have them in the following order
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(SR,ER,FR). For the second case set
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er-offset = <1>.
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- unused-units : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set to turn off unused
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devices.
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- idle-doze : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set to turn off unused
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devices. This is usually just CPM[CPU].
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- standby : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set on standby and
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restored on resume.
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- suspend : specifier consist of one cell. For each
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bit in the cell, the corresponding bit
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in CPM will be set on suspend (mem) and
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restored on resume. Note, for standby
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and suspend the corresponding bits can
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be different or the same. Usually for
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standby only class 2 and 3 units are set.
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However, the interface does not care.
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If they are the same, the additional
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power saving will be seeing if support
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is available to put the DDR in self
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refresh mode and any additional power
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saving techniques for the specific SoC.
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Example:
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CPM0: cpm {
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compatible = "ibm,cpm";
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dcr-access-method = "native";
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dcr-reg = <0x160 0x003>;
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er-offset = <0>;
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unused-units = <0x00000100>;
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idle-doze = <0x02000000>;
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standby = <0xfeff0000>;
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suspend = <0xfeff791d>;
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};
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