58 lines
1.8 KiB
Plaintext
58 lines
1.8 KiB
Plaintext
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Socionext UniPhier USB3 Super-Speed (SS) PHY
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This describes the devicetree bindings for PHY interfaces built into
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USB3 controller implemented on Socionext UniPhier SoCs.
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Although the controller includes High-Speed PHY and Super-Speed PHY,
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this describes about Super-Speed PHY.
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Required properties:
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- compatible: Should contain one of the following:
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"socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
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"socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
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"socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
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"socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
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- reg: Specifies offset and length of the register set for the device.
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- #phy-cells: Should be 0.
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- clocks: A list of phandles to the clock gate for USB3 glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names:
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"gio", "link" - for Pro4 SoC
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"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
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"phy", "link" - for others
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- resets: A list of phandles to the reset control for USB3 glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names:
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"gio", "link" - for Pro4 SoC
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"phy", "link" - for others
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Optional properties:
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- vbus-supply: A phandle to the regulator for USB VBUS.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Example:
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_vbus0: regulator {
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...
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};
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usb_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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};
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...
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};
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