72 lines
2.0 KiB
Plaintext
72 lines
2.0 KiB
Plaintext
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Device tree bindings for HiSilicon INNO USB2 PHY
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Required properties:
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- compatible: Should be one of the following strings:
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"hisilicon,inno-usb2-phy",
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"hisilicon,hi3798cv200-usb2-phy".
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- reg: Should be the address space for PHY configuration register in peripheral
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controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
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- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
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reference clock.
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- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
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signal.
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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The INNO USB2 PHY device should be a child node of peripheral controller that
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contains the PHY configuration register, and each device suppports up to 2 PHY
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ports which are represented as child nodes of INNO USB2 PHY device.
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Required properties for PHY port node:
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- reg: The PHY port instance number.
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- #phy-cells: Defined by generic PHY bindings. Must be 0.
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- resets: The phandle and reset specifier pair for PHY port reset signal.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties
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Example:
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perictrl: peripheral-controller@8a20000 {
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compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
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reg = <0x8a20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8a20000 0x1000>;
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usb2_phy1: usb2-phy@120 {
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compatible = "hisilicon,hi3798cv200-usb2-phy";
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reg = <0x120 0x4>;
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clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
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resets = <&crg 0xbc 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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usb2_phy1_port0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 8>;
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};
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usb2_phy1_port1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 9>;
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};
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};
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usb2_phy2: usb2-phy@124 {
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compatible = "hisilicon,hi3798cv200-usb2-phy";
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reg = <0x124 0x4>;
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clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
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resets = <&crg 0xbc 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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usb2_phy2_port0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 10>;
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};
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};
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};
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