30 lines
929 B
Plaintext
30 lines
929 B
Plaintext
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Mixel DSI PHY for i.MX8
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The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
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MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
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electrical signals for DSI.
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Required properties:
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- compatible: Must be:
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- "fsl,imx8mq-mipi-dphy"
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "phy_ref": phandle and specifier referring to the DPHY ref clock
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- reg: the register range of the PHY controller
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- #phy-cells: number of cells in PHY, as defined in
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Documentation/devicetree/bindings/phy/phy-bindings.txt
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this must be <0>
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Optional properties:
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- power-domains: phandle to power domain
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Example:
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dphy: dphy@30a0030 {
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compatible = "fsl,imx8mq-mipi-dphy";
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clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
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clock-names = "phy_ref";
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reg = <0x30a00300 0x100>;
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power-domains = <&pd_mipi0>;
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#phy-cells = <0>;
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};
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