82 lines
2.8 KiB
Plaintext
82 lines
2.8 KiB
Plaintext
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Socionext UniPhier PCIe host controller bindings
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This describes the devicetree bindings for PCIe host controller implemented
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on Socionext UniPhier SoCs.
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UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Required properties:
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- compatible: Should be "socionext,uniphier-pcie".
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- reg: Specifies offset and length of the register set for the device.
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According to the reg-names, appropriate register sets are required.
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- reg-names: Must include the following entries:
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"dbi" - controller configuration registers
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"link" - SoC-specific glue layer registers
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"config" - PCIe configuration space
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- clocks: A phandle to the clock gate for PCIe glue layer including
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the host controller.
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- resets: A phandle to the reset line for PCIe glue layer including
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the host controller.
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- interrupts: A list of interrupt specifiers. According to the
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interrupt-names, appropriate interrupts are required.
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- interrupt-names: Must include the following entries:
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"dma" - DMA interrupt
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"msi" - MSI interrupt
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Optional properties:
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- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
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phys are required.
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- phy-names: Must be "pcie-phy".
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Required sub-node:
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- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
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interrupts.
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Required properties for legacy-interrupt-controller:
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- interrupt-controller: identifies the node as an interrupt controller.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-parent: Phandle to the parent interrupt controller.
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- interrupts: An interrupt specifier for legacy interrupt.
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Example:
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pcie: pcie@66000000 {
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compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
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status = "disabled";
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reg-names = "dbi", "link", "config";
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reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
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<0x2fff0000 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&sys_clk 24>;
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resets = <&sys_rst 24>;
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num-lanes = <1>;
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num-viewport = <1>;
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bus-range = <0x0 0xff>;
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device_type = "pci";
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ranges =
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/* downstream I/O */
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<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
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#interrupt-cells = <1>;
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interrupt-names = "dma", "msi";
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interrupts = <0 224 4>, <0 225 4>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
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<0 0 0 2 &pcie_intc 1>, /* INTB */
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<0 0 0 3 &pcie_intc 2>, /* INTC */
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<0 0 0 4 &pcie_intc 3>; /* INTD */
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <0 226 4>;
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};
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};
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