130 lines
2.6 KiB
Plaintext
130 lines
2.6 KiB
Plaintext
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Generic register bitfield-based multiplexer controller bindings
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Define register bitfields to be used to control multiplexers. The parent
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device tree node must be a device node to provide register r/w access.
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Required properties:
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- compatible : should be one of
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"reg-mux" : if parent device of mux controller is not syscon device
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"mmio-mux" : if parent device of mux controller is syscon device
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- #mux-control-cells : <1>
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- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
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pairs, each describing a single mux control.
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* Standard mux-controller bindings as decribed in mux-controller.txt
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Optional properties:
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- idle-states : if present, the state the muxes will have when idle. The
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special state MUX_IDLE_AS_IS is the default.
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The multiplexer state of each multiplexer is defined as the value of the
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bitfield described by the corresponding register offset and bitfield mask
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pair in the mux-reg-masks array.
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Example 1:
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The parent device of mux controller is not a syscon device.
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&i2c0 {
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fpga@66 { // fpga connected to i2c
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compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
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"simple-mfd";
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reg = <0x66>;
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mux: mux-controller {
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compatible = "reg-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
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<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
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};
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};
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};
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mdio-mux-1 {
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compatible = "mdio-mux-multiplexer";
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mux-controls = <&mux 0>;
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mdio-parent-bus = <&emdio1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio@8 {
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reg = <0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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..
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..
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};
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mdio-mux-2 {
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compatible = "mdio-mux-multiplexer";
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mux-controls = <&mux 1>;
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mdio-parent-bus = <&emdio2>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mdio@1 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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..
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..
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};
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Example 2:
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The parent device of mux controller is syscon device.
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syscon {
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compatible = "syscon";
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mux: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
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<0x3 0x40>, /* 1: reg 0x3, bit 6 */
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idle-states = <MUX_IDLE_AS_IS>, <0>;
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};
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};
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video-mux {
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compatible = "video-mux";
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mux-controls = <&mux 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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/* inputs 0..3 */
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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port@2 {
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reg = <2>;
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};
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port@3 {
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reg = <3>;
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};
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/* output */
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port@4 {
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reg = <4>;
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};
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};
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};
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