77 lines
2.8 KiB
Plaintext
77 lines
2.8 KiB
Plaintext
|
* Qualcomm SDHCI controller (sdhci-msm)
|
||
|
|
|
||
|
|
This file documents differences between the core properties in mmc.txt
|
||
|
|
and the properties used by the sdhci-msm driver.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible: Should contain a SoC-specific string and a IP version string:
|
||
|
|
version strings:
|
||
|
|
"qcom,sdhci-msm-v4" for sdcc versions less than 5.0
|
||
|
|
"qcom,sdhci-msm-v5" for sdcc version 5.0
|
||
|
|
For SDCC version 5.0.0, MCI registers are removed from SDCC
|
||
|
|
interface and some registers are moved to HC. New compatible
|
||
|
|
string is added to support this change - "qcom,sdhci-msm-v5".
|
||
|
|
full compatible strings with SoC and version:
|
||
|
|
"qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
|
||
|
|
"qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
|
||
|
|
"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
|
||
|
|
"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
|
||
|
|
"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
|
||
|
|
"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
|
||
|
|
"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
|
||
|
|
NOTE that some old device tree files may be floating around that only
|
||
|
|
have the string "qcom,sdhci-msm-v4" without the SoC compatible string
|
||
|
|
but doing that should be considered a deprecated practice.
|
||
|
|
|
||
|
|
- reg: Base address and length of the register in the following order:
|
||
|
|
- Host controller register map (required)
|
||
|
|
- SD Core register map (required for msm-v4 and below)
|
||
|
|
- interrupts: Should contain an interrupt-specifiers for the interrupts:
|
||
|
|
- Host controller interrupt (required)
|
||
|
|
- pinctrl-names: Should contain only one value - "default".
|
||
|
|
- pinctrl-0: Should specify pin control groups used for this controller.
|
||
|
|
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
|
||
|
|
- clock-names: Should contain the following:
|
||
|
|
"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
|
||
|
|
"core" - SDC MMC clock (MCLK) (required)
|
||
|
|
"bus" - SDCC bus voter clock (optional)
|
||
|
|
"xo" - TCXO clock (optional)
|
||
|
|
"cal" - reference clock for RCLK delay calibration (optional)
|
||
|
|
"sleep" - sleep clock for RCLK delay calibration (optional)
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
sdhc_1: sdhci@f9824900 {
|
||
|
|
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
|
||
|
|
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
|
||
|
|
interrupts = <0 123 0>;
|
||
|
|
bus-width = <8>;
|
||
|
|
non-removable;
|
||
|
|
|
||
|
|
vmmc-supply = <&pm8941_l20>;
|
||
|
|
vqmmc-supply = <&pm8941_s3>;
|
||
|
|
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
|
||
|
|
clock-names = "core", "iface";
|
||
|
|
};
|
||
|
|
|
||
|
|
sdhc_2: sdhci@f98a4900 {
|
||
|
|
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
|
||
|
|
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
|
||
|
|
interrupts = <0 125 0>;
|
||
|
|
bus-width = <4>;
|
||
|
|
cd-gpios = <&msmgpio 62 0x1>;
|
||
|
|
|
||
|
|
vmmc-supply = <&pm8941_l21>;
|
||
|
|
vqmmc-supply = <&pm8941_l13>;
|
||
|
|
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
|
||
|
|
|
||
|
|
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
|
||
|
|
clock-names = "core", "iface";
|
||
|
|
};
|