73 lines
3.2 KiB
Plaintext
73 lines
3.2 KiB
Plaintext
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* MTK MMC controller
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The MTK MSDC can act as a MMC controller
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to support MMC, SD, and SDIO types of memory cards.
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This file documents differences between the core properties in mmc.txt
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and the properties used by the msdc driver.
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Required properties:
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- compatible: value should be either of the following.
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"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
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"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
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"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
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"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
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"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
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"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
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"mediatek,mt7622-mmc": for MT7622 SoC
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"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
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"mediatek,mt7620-mmc", for MT7621 SoC (and others)
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- reg: physical base address of the controller and length
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- interrupts: Should contain MSDC interrupt number
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- clocks: Should contain phandle for the clock feeding the MMC controller
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- clock-names: Should contain the following:
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"source" - source clock (required)
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"hclk" - HCLK which used for host (required)
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"source_cg" - independent source clock gate (required for MT2712)
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"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
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- pinctrl-names: should be "default", "state_uhs"
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- pinctrl-0: should contain default/high speed pin ctrl
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- pinctrl-1: should contain uhs mode pin ctrl
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- vmmc-supply: power to the Core
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- vqmmc-supply: power to the IO
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Optional properties:
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- assigned-clocks: PLL of the source clock
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- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
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- hs400-ds-delay: HS400 DS delay setting
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- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
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If present,HS400 command responses are sampled on rising edges.
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If not present,HS400 command responses are sampled on falling edges.
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- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
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error caused by stop clock(fifo full)
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Valid range = [0:0x7]. if not present, default value is 0.
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applied to compatible "mediatek,mt2701-mmc".
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Examples:
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
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reg = <0 0x11230000 0 0x108>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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vmmc-supply = <&mt6397_vemc_3v3_reg>;
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vqmmc-supply = <&mt6397_vio18_reg>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
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clock-names = "source", "hclk";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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hs400-ds-delay = <0x14015>;
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mediatek,hs200-cmd-int-delay = <26>;
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mediatek,hs400-cmd-int-delay = <14>;
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mediatek,hs400-cmd-resp-sel-rising;
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};
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