36 lines
955 B
Plaintext
36 lines
955 B
Plaintext
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Freescale Multi Mode DDR controller (MMDC)
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Required properties :
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- compatible : should be one of following:
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for i.MX6Q/i.MX6DL:
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- "fsl,imx6q-mmdc";
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for i.MX6QP:
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- "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
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for i.MX6SL:
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- "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
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for i.MX6SLL:
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- "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
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for i.MX6SX:
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- "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
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for i.MX6UL/i.MX6ULL/i.MX6ULZ:
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- "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
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for i.MX7ULP:
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- "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
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- reg : address and size of MMDC DDR controller registers
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Optional properties :
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- clocks : the clock provided by the SoC to access the MMDC registers
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Example :
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mmdc0: memory-controller@21b0000 { /* MMDC0 */
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compatible = "fsl,imx6q-mmdc";
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reg = <0x021b0000 0x4000>;
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clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
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};
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mmdc1: memory-controller@21b4000 { /* MMDC1 */
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compatible = "fsl,imx6q-mmdc";
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reg = <0x021b4000 0x4000>;
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status = "disabled";
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};
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