44 lines
1.5 KiB
Plaintext
44 lines
1.5 KiB
Plaintext
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DT bindings for the Renesas RZ/A1 Interrupt Controller
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The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
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RZ/A1 and RZ/A2 SoCs:
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- IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
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interrupts,
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- NMI edge select.
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Required properties:
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- compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
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fallback.
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Examples with soctypes are:
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- "renesas,r7s72100-irqc" (RZ/A1H)
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- "renesas,r7s9210-irqc" (RZ/A2M)
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- #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
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in interrupts.txt in this directory)
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- #address-cells: Must be zero
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- interrupt-controller: Marks the device as an interrupt controller
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- reg: Base address and length of the memory resource used by the interrupt
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controller
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- interrupt-map: Specifies the mapping from external interrupts to GIC
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interrupts
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- interrupt-map-mask: Must be <7 0>
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Example:
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irqc: interrupt-controller@fcfef800 {
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compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xfcfef800 0x6>;
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interrupt-map =
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<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <7 0>;
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};
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