86 lines
2.8 KiB
Plaintext
86 lines
2.8 KiB
Plaintext
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Analog Devices ADIS16480 and similar IMUs
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Required properties for the ADIS16480:
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- compatible: Must be one of
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* "adi,adis16375"
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* "adi,adis16480"
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* "adi,adis16485"
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* "adi,adis16488"
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* "adi,adis16495-1"
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* "adi,adis16495-2"
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* "adi,adis16495-3"
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* "adi,adis16497-1"
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* "adi,adis16497-2"
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* "adi,adis16497-3"
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- reg: SPI chip select number for the device
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- spi-max-frequency: Max SPI frequency to use
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see: Documentation/devicetree/bindings/spi/spi-bus.txt
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- spi-cpha: See Documentation/devicetree/bindings/spi/spi-bus.txt
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- spi-cpol: See Documentation/devicetree/bindings/spi/spi-bus.txt
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- interrupts: interrupt mapping for IRQ, accepted values are:
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* IRQF_TRIGGER_RISING
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* IRQF_TRIGGER_FALLING
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Optional properties:
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- interrupt-names: Data ready line selection. Valid values are:
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* DIO1
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* DIO2
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* DIO3
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* DIO4
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If this field is left empty, DIO1 is assigned as default data ready
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signal.
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- reset-gpios: must be the device tree identifier of the RESET pin. As the line
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is active low, it should be marked GPIO_ACTIVE_LOW.
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- clocks: phandle to the external clock. Should be set according to
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"clock-names".
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If this field is left empty together with the "clock-names" field, then
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the internal clock is used.
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- clock-names: The name of the external clock to be used. Valid values are:
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* sync: In sync mode, the internal clock is disabled and the frequency
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of the external clock signal establishes therate of data
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collection and processing. See Fig 14 and 15 in the datasheet.
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The clock-frequency must be:
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* 3000 to 4500 Hz for adis1649x devices.
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* 700 to 2400 Hz for adis1648x devices.
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* pps: In Pulse Per Second (PPS) Mode, the rate of data collection and
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production is equal to the product of the external clock
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frequency and the scale factor in the SYNC_SCALE register, see
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Table 154 in the datasheet.
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The clock-frequency must be:
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* 1 to 128 Hz for adis1649x devices.
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* This mode is not supported by adis1648x devices.
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If this field is left empty together with the "clocks" field, then the
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internal clock is used.
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- adi,ext-clk-pin: The DIOx line to be used as an external clock input.
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Valid values are:
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* DIO1
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* DIO2
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* DIO3
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* DIO4
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Each DIOx pin supports only one function at a time (data ready line
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selection or external clock input). When a single pin has two
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two assignments, the enable bit for the lower priority function
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automatically resets to zero (disabling the lower priority function).
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Data ready has highest priority.
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If this field is left empty, DIO2 is assigned as default external clock
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input pin.
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Example:
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imu@0 {
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compatible = "adi,adis16495-1";
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reg = <0>;
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spi-max-frequency = <3200000>;
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spi-cpol;
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spi-cpha;
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interrupts = <25 IRQF_TRIGGER_FALLING>;
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interrupt-parent = <&gpio>;
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interrupt-names = "DIO2";
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clocks = <&adis16495_sync>;
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clock-names = "sync";
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adi,ext-clk-pin = "DIO1";
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};
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