75 lines
2.7 KiB
Plaintext
75 lines
2.7 KiB
Plaintext
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Device tree configuration for i2c-ocores
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Required properties:
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- compatible : "opencores,i2c-ocores"
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"aeroflexgaisler,i2cmst"
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"sifive,fu540-c000-i2c", "sifive,i2c0"
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For Opencore based I2C IP block reimplemented in
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FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
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for additional details.
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- reg : bus address start and address range size of device
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- clocks : handle to the controller clock; see the note below.
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Mutually exclusive with opencores,ip-clock-frequency
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- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
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see the note below. Mutually exclusive with clocks
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- #address-cells : should be <1>
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- #size-cells : should be <0>
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Optional properties:
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- interrupts : interrupt number.
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- clock-frequency : frequency of bus clock in Hz; see the note below.
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Defaults to 100 KHz when the property is not specified
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- reg-shift : device register offsets are shifted by this value
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- reg-io-width : io register width in bytes (1, 2 or 4)
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- regstep : deprecated, use reg-shift above
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Note
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clock-frequency property is meant to control the bus frequency for i2c bus
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drivers, but it was incorrectly used to specify i2c controller input clock
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frequency. So the following rules are set to fix this situation:
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- if clock-frequency is present and neither opencores,ip-clock-frequency nor
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clocks are, then clock-frequency specifies i2c controller clock frequency.
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This is to keep backwards compatibility with setups using old DTB. i2c bus
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frequency is fixed at 100 KHz.
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- if clocks is present it specifies i2c controller clock. clock-frequency
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property specifies i2c bus frequency.
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- if opencores,ip-clock-frequency is present it specifies i2c controller
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clock frequency. clock-frequency property specifies i2c bus frequency.
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Examples:
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i2c0: ocores@a0000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "opencores,i2c-ocores";
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reg = <0xa0000000 0x8>;
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interrupts = <10>;
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opencores,ip-clock-frequency = <20000000>;
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reg-shift = <0>; /* 8 bit registers */
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reg-io-width = <1>; /* 8 bit read/write */
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dummy@60 {
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compatible = "dummy";
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reg = <0x60>;
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};
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};
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or
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i2c0: ocores@a0000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "opencores,i2c-ocores";
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reg = <0xa0000000 0x8>;
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interrupts = <10>;
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clocks = <&osc>;
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clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
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reg-shift = <0>; /* 8 bit registers */
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reg-io-width = <1>; /* 8 bit read/write */
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dummy@60 {
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compatible = "dummy";
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reg = <0x60>;
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};
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};
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