112 lines
4.1 KiB
Plaintext
112 lines
4.1 KiB
Plaintext
|
* STMicroelectronics STM32 DMA controller
|
||
|
|
|
||
|
|
The STM32 DMA is a general-purpose direct memory access controller capable of
|
||
|
|
supporting 8 independent DMA channels. Each channel can have up to 8 requests.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible: Should be "st,stm32-dma"
|
||
|
|
- reg: Should contain DMA registers location and length. This should include
|
||
|
|
all of the per-channel registers.
|
||
|
|
- interrupts: Should contain all of the per-channel DMA interrupts in
|
||
|
|
ascending order with respect to the DMA channel index.
|
||
|
|
- clocks: Should contain the input clock of the DMA instance.
|
||
|
|
- #dma-cells : Must be <4>. See DMA client paragraph for more details.
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
- dma-requests : Number of DMA requests supported.
|
||
|
|
- resets: Reference to a reset controller asserting the DMA controller
|
||
|
|
- st,mem2mem: boolean; if defined, it indicates that the controller supports
|
||
|
|
memory-to-memory transfer
|
||
|
|
- dmas: A list of eight dma specifiers, one for each entry in dma-names.
|
||
|
|
Refer to stm32-mdma.txt for more details.
|
||
|
|
- dma-names: should contain "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6" and
|
||
|
|
"ch7" and represents each STM32 DMA channel connected to a STM32 MDMA one.
|
||
|
|
- memory-region : phandle to a node describing memory to be used for
|
||
|
|
M2M intermediate transfer between DMA and MDMA.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
dma2: dma-controller@40026400 {
|
||
|
|
compatible = "st,stm32-dma";
|
||
|
|
reg = <0x40026400 0x400>;
|
||
|
|
interrupts = <56>,
|
||
|
|
<57>,
|
||
|
|
<58>,
|
||
|
|
<59>,
|
||
|
|
<60>,
|
||
|
|
<68>,
|
||
|
|
<69>,
|
||
|
|
<70>;
|
||
|
|
clocks = <&clk_hclk>;
|
||
|
|
#dma-cells = <4>;
|
||
|
|
st,mem2mem;
|
||
|
|
resets = <&rcc 150>;
|
||
|
|
dma-requests = <8>;
|
||
|
|
dmas = <&mdma1 8 0x10 0x1200000a 0x40026408 0x00000020 1>,
|
||
|
|
<&mdma1 9 0x10 0x1200000a 0x40026408 0x00000800 1>,
|
||
|
|
<&mdma1 10 0x10 0x1200000a 0x40026408 0x00200000 1>,
|
||
|
|
<&mdma1 11 0x10 0x1200000a 0x40026408 0x08000000 1>,
|
||
|
|
<&mdma1 12 0x10 0x1200000a 0x4002640C 0x00000020 1>,
|
||
|
|
<&mdma1 13 0x10 0x1200000a 0x4002640C 0x00000800 1>,
|
||
|
|
<&mdma1 14 0x10 0x1200000a 0x4002640C 0x00200000 1>,
|
||
|
|
<&mdma1 15 0x10 0x1200000a 0x4002640C 0x08000000 1>;
|
||
|
|
dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
|
||
|
|
memory-region = <&sram_dmapool>;
|
||
|
|
};
|
||
|
|
|
||
|
|
* DMA client
|
||
|
|
|
||
|
|
DMA clients connected to the STM32 DMA controller must use the format
|
||
|
|
described in the dma.txt file, using a four-cell specifier for each
|
||
|
|
channel: a phandle to the DMA controller plus the following four integer cells:
|
||
|
|
|
||
|
|
1. The channel id
|
||
|
|
2. The request line number
|
||
|
|
3. A 32bit mask specifying the DMA channel configuration which are device
|
||
|
|
dependent:
|
||
|
|
-bit 9: Peripheral Increment Address
|
||
|
|
0x0: no address increment between transfers
|
||
|
|
0x1: increment address between transfers
|
||
|
|
-bit 10: Memory Increment Address
|
||
|
|
0x0: no address increment between transfers
|
||
|
|
0x1: increment address between transfers
|
||
|
|
-bit 15: Peripheral Increment Offset Size
|
||
|
|
0x0: offset size is linked to the peripheral bus width
|
||
|
|
0x1: offset size is fixed to 4 (32-bit alignment)
|
||
|
|
-bit 16-17: Priority level
|
||
|
|
0x0: low
|
||
|
|
0x1: medium
|
||
|
|
0x2: high
|
||
|
|
0x3: very high
|
||
|
|
4. A bitfield value specifying DMA features which are device dependent:
|
||
|
|
-bit 0-1: DMA FIFO threshold selection
|
||
|
|
0x0: 1/4 full FIFO
|
||
|
|
0x1: 1/2 full FIFO
|
||
|
|
0x2: 3/4 full FIFO
|
||
|
|
0x3: full FIFO
|
||
|
|
-bit 2: DMA direct mode
|
||
|
|
0: FIFO mode: with threshold level selectable with bit 0-1
|
||
|
|
1: Direct mode: each DMA request immediately initiates a transfer
|
||
|
|
from/to the memory.
|
||
|
|
-bit 30-29: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
|
||
|
|
Order is given by those 2 bits starting at 0.
|
||
|
|
Valid only whether Intermediate M2M transfer is set.
|
||
|
|
For cyclic, whether Intermediate M2M transfer is chosen, any value can
|
||
|
|
be set: SRAM buffer size will rely on period size and not on this DT
|
||
|
|
value.
|
||
|
|
-bit 31: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
|
||
|
|
0: MDMA not used to generate an intermediate M2M transfer
|
||
|
|
1: MDMA used to generate an intermediate M2M transfer.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
usart1: serial@40011000 {
|
||
|
|
compatible = "st,stm32-uart";
|
||
|
|
reg = <0x40011000 0x400>;
|
||
|
|
interrupts = <37>;
|
||
|
|
clocks = <&clk_pclk2>;
|
||
|
|
dmas = <&dma2 2 4 0x10400 0x1>,
|
||
|
|
<&dma2 7 5 0x10200 0x1>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
};
|