87 lines
2.4 KiB
Plaintext
87 lines
2.4 KiB
Plaintext
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Qualcomm adreno/snapdragon GPU
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Required properties:
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- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
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"amd,imageon-XYZ.W", "amd,imageon"
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for example: "qcom,adreno-306.0", "qcom,adreno"
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Note that you need to list the less specific "qcom,adreno" (since this
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is what the device is matched on), in addition to the more specific
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with the chip-id.
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If "amd,imageon" is used, there should be no top level msm device.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt signal from the gpu.
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- clocks: device clocks (if applicable)
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See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required by a3xx, a4xx and a5xx
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cores:
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* "core"
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* "iface"
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* "mem_iface"
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For GMU attached devices the GPU clocks are not used and are not required. The
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following devices should not list clocks:
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- qcom,adreno-630.2
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- iommus: optional phandle to an adreno iommu instance
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- operating-points-v2: optional phandle to the OPP operating points
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- interconnects: optional phandle to an interconnect provider. See
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../interconnect/interconnect.txt for details.
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- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
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control the power for the GPU. Applicable targets:
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- qcom,adreno-630.2
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- zap-shader: For a5xx and a6xx devices this node contains a memory-region that
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points to reserved memory to store the zap shader that can be used to help
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bring the GPU out of secure mode.
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Example 3xx/4xx/a5xx:
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/ {
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...
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gpu: qcom,kgsl-3d0@4300000 {
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compatible = "qcom,adreno-320.2", "qcom,adreno";
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reg = <0x04300000 0x20000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <GIC_SPI 80 0>;
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clock-names =
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"core",
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"iface",
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"mem_iface";
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clocks =
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<&mmcc GFX3D_CLK>,
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<&mmcc GFX3D_AHB_CLK>,
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<&mmcc MMSS_IMEM_AHB_CLK>;
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};
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};
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Example a6xx (with GMU):
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/ {
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...
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gpu@5000000 {
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compatible = "qcom,adreno-630.2", "qcom,adreno";
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#stream-id-cells = <16>;
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reg = <0x5000000 0x40000>, <0x509e000 0x10>;
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reg-names = "kgsl_3d0_reg_memory", "cx_mem";
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/*
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* Look ma, no clocks! The GPU clocks and power are
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* controlled entirely by the GMU
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*/
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&adreno_smmu 0>;
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operating-points-v2 = <&gpu_opp_table>;
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interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
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qcom,gmu = <&gmu>;
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zap-shader {
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memory-region = <&zap_shader_region>;
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};
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};
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};
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