66 lines
1.8 KiB
Plaintext
66 lines
1.8 KiB
Plaintext
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Qualcomm adreno/snapdragon GMU (Graphics management unit)
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The GMU is a programmable power controller for the GPU. the CPU controls the
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GMU which in turn handles power controls for the GPU.
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Required properties:
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- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
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for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
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Note that you need to list the less specific "qcom,adreno-gmu"
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for generic matches and the more specific identifier to identify
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the specific device.
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- reg: Physical base address and length of the GMU registers.
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- reg-names: Matching names for the register regions
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* "gmu"
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* "gmu_pdc"
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* "gmu_pdc_seg"
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- interrupts: The interrupt signals from the GMU.
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- interrupt-names: Matching names for the interrupts
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* "hfi"
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* "gmu"
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- clocks: phandles to the device clocks
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- clock-names: Matching names for the clocks
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* "gmu"
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* "cxo"
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* "axi"
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* "mnoc"
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- power-domains: should be:
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<&clock_gpucc GPU_CX_GDSC>
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<&clock_gpucc GPU_GX_GDSC>
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- power-domain-names: Matching names for the power domains
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- iommus: phandle to the adreno iommu
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- operating-points-v2: phandle to the OPP operating points
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Example:
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/ {
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...
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gmu: gmu@506a000 {
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compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
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reg = <0x506a000 0x30000>,
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<0xb280000 0x10000>,
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<0xb480000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gmu", "cxo", "axi", "memnoc";
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power-domains = <&gpucc GPU_CX_GDSC>,
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<&gpucc GPU_GX_GDSC>;
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power-domain-names = "cx", "gx";
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iommus = <&adreno_smmu 5>;
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operating-points-v2 = <&gmu_opp_table>;
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};
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};
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