249 lines
6.2 KiB
C
249 lines
6.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
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*
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* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/* Transmitter HS Pre-Emphasis Enable */
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#define RCU_CFG1_TX_PEE BIT(0)
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/* Disconnect Threshold */
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#define RCU_CFG1_DIS_THR_MASK 0x00038000
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#define RCU_CFG1_DIS_THR_SHIFT 15
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struct ltq_rcu_usb2_bits {
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u8 hostmode;
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u8 slave_endianness;
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u8 host_endianness;
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bool have_ana_cfg;
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};
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struct ltq_rcu_usb2_priv {
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struct regmap *regmap;
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unsigned int phy_reg_offset;
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unsigned int ana_cfg1_reg_offset;
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const struct ltq_rcu_usb2_bits *reg_bits;
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struct device *dev;
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struct phy *phy;
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struct clk *phy_gate_clk;
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struct reset_control *ctrl_reset;
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struct reset_control *phy_reset;
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};
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static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
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.hostmode = 11,
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.slave_endianness = 9,
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.host_endianness = 10,
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.have_ana_cfg = false,
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};
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static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
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.hostmode = 11,
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.slave_endianness = 17,
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.host_endianness = 10,
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.have_ana_cfg = false,
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};
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static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
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.hostmode = 11,
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.slave_endianness = 9,
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.host_endianness = 10,
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.have_ana_cfg = true,
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};
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static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
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{
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.compatible = "lantiq,ase-usb2-phy",
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.data = &xway_rcu_usb2_reg_bits,
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},
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{
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.compatible = "lantiq,danube-usb2-phy",
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.data = &xway_rcu_usb2_reg_bits,
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},
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{
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.compatible = "lantiq,xrx100-usb2-phy",
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.data = &xrx100_rcu_usb2_reg_bits,
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},
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{
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.compatible = "lantiq,xrx200-usb2-phy",
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.data = &xrx200_rcu_usb2_reg_bits,
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},
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{
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.compatible = "lantiq,xrx300-usb2-phy",
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.data = &xrx200_rcu_usb2_reg_bits,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
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static int ltq_rcu_usb2_phy_init(struct phy *phy)
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{
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struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
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if (priv->reg_bits->have_ana_cfg) {
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regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
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RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
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regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
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RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
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}
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/* Configure core to host mode */
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regmap_update_bits(priv->regmap, priv->phy_reg_offset,
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BIT(priv->reg_bits->hostmode), 0);
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/* Select DMA endianness (Host-endian: big-endian) */
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regmap_update_bits(priv->regmap, priv->phy_reg_offset,
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BIT(priv->reg_bits->slave_endianness), 0);
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regmap_update_bits(priv->regmap, priv->phy_reg_offset,
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BIT(priv->reg_bits->host_endianness),
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BIT(priv->reg_bits->host_endianness));
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return 0;
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}
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static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
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{
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struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
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struct device *dev = priv->dev;
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int ret;
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reset_control_deassert(priv->phy_reset);
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ret = clk_prepare_enable(priv->phy_gate_clk);
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if (ret)
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dev_err(dev, "failed to enable PHY gate\n");
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return ret;
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}
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static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
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{
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struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
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reset_control_assert(priv->phy_reset);
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clk_disable_unprepare(priv->phy_gate_clk);
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return 0;
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}
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static struct phy_ops ltq_rcu_usb2_phy_ops = {
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.init = ltq_rcu_usb2_phy_init,
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.power_on = ltq_rcu_usb2_phy_power_on,
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.power_off = ltq_rcu_usb2_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int ltq_rcu_usb2_of_parse(struct ltq_rcu_usb2_priv *priv,
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struct platform_device *pdev)
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{
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struct device *dev = priv->dev;
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const __be32 *offset;
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priv->reg_bits = of_device_get_match_data(dev);
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priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
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if (IS_ERR(priv->regmap)) {
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dev_err(dev, "Failed to lookup RCU regmap\n");
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return PTR_ERR(priv->regmap);
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}
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offset = of_get_address(dev->of_node, 0, NULL, NULL);
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if (!offset) {
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dev_err(dev, "Failed to get RCU PHY reg offset\n");
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return -ENOENT;
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}
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priv->phy_reg_offset = __be32_to_cpu(*offset);
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if (priv->reg_bits->have_ana_cfg) {
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offset = of_get_address(dev->of_node, 1, NULL, NULL);
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if (!offset) {
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dev_err(dev, "Failed to get RCU ANA CFG1 reg offset\n");
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return -ENOENT;
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}
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priv->ana_cfg1_reg_offset = __be32_to_cpu(*offset);
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}
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priv->phy_gate_clk = devm_clk_get(dev, "phy");
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if (IS_ERR(priv->phy_gate_clk)) {
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dev_err(dev, "Unable to get USB phy gate clk\n");
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return PTR_ERR(priv->phy_gate_clk);
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}
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priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
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if (IS_ERR(priv->ctrl_reset)) {
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if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER)
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dev_err(dev, "failed to get 'ctrl' reset\n");
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return PTR_ERR(priv->ctrl_reset);
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}
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priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
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return PTR_ERR_OR_ZERO(priv->phy_reset);
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}
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static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ltq_rcu_usb2_priv *priv;
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struct phy_provider *provider;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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ret = ltq_rcu_usb2_of_parse(priv, pdev);
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if (ret)
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return ret;
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/* Reset USB core through reset controller */
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reset_control_deassert(priv->ctrl_reset);
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reset_control_assert(priv->phy_reset);
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priv->phy = devm_phy_create(dev, dev->of_node, <q_rcu_usb2_phy_ops);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(priv->phy);
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}
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phy_set_drvdata(priv->phy, priv);
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(provider))
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return PTR_ERR(provider);
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dev_set_drvdata(priv->dev, priv);
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return 0;
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}
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static struct platform_driver ltq_rcu_usb2_phy_driver = {
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.probe = ltq_rcu_usb2_phy_probe,
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.driver = {
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.name = "lantiq-rcu-usb2-phy",
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.of_match_table = ltq_rcu_usb2_phy_of_match,
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}
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};
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module_platform_driver(ltq_rcu_usb2_phy_driver);
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
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MODULE_LICENSE("GPL v2");
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