536 lines
14 KiB
C
536 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Ludovic.barre@st.com for STMicroelectronics.
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/of_address.h>
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#include <linux/reset.h>
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#include <linux/scatterlist.h>
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#include "mmci.h"
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#define SDMMC_LLI_BUF_LEN PAGE_SIZE
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#define SDMMC_IDMA_BURST BIT(MMCI_STM32_IDMABNDT_SHIFT)
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#define DLYB_CR 0x0
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#define DLYB_CR_DEN BIT(0)
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#define DLYB_CR_SEN BIT(1)
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#define DLYB_CFGR 0x4
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#define DLYB_CFGR_SEL_MASK GENMASK(3, 0)
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#define DLYB_CFGR_UNIT_MASK GENMASK(14, 8)
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#define DLYB_CFGR_LNG_MASK GENMASK(27, 16)
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#define DLYB_CFGR_LNGF BIT(31)
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#define DLYB_CFGR_SEL_MAX 12
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#define DLYB_CFGR_UNIT_MAX 127
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struct sdmmc_lli_desc {
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u32 idmalar;
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u32 idmabase;
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u32 idmasize;
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};
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struct sdmmc_idma {
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dma_addr_t sg_dma;
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void *sg_cpu;
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};
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struct sdmmc_dlyb {
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void __iomem *base;
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u32 unit;
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u32 max;
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};
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int sdmmc_idma_validate_data(struct mmci_host *host,
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struct mmc_data *data)
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{
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struct scatterlist *sg;
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int i;
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/*
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* idma has constraints on idmabase & idmasize for each element
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* excepted the last element which has no constraint on idmasize
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*/
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for_each_sg(data->sg, sg, data->sg_len - 1, i) {
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if (!IS_ALIGNED(data->sg->offset, sizeof(u32)) ||
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!IS_ALIGNED(data->sg->length, SDMMC_IDMA_BURST)) {
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dev_err(mmc_dev(host->mmc),
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"unaligned scatterlist: ofst:%x length:%d\n",
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data->sg->offset, data->sg->length);
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return -EINVAL;
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}
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}
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if (!IS_ALIGNED(data->sg->offset, sizeof(u32))) {
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dev_err(mmc_dev(host->mmc),
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"unaligned last scatterlist: ofst:%x length:%d\n",
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data->sg->offset, data->sg->length);
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return -EINVAL;
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}
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return 0;
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}
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static int _sdmmc_idma_prep_data(struct mmci_host *host,
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struct mmc_data *data)
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{
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int n_elem;
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n_elem = dma_map_sg(mmc_dev(host->mmc),
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data->sg,
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data->sg_len,
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mmc_get_dma_dir(data));
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if (!n_elem) {
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dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
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return -EINVAL;
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}
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return 0;
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}
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static int sdmmc_idma_prep_data(struct mmci_host *host,
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struct mmc_data *data, bool next)
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{
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/* Check if job is already prepared. */
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if (!next && data->host_cookie == host->next_cookie)
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return 0;
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return _sdmmc_idma_prep_data(host, data);
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}
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static void sdmmc_idma_unprep_data(struct mmci_host *host,
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struct mmc_data *data, int err)
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{
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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mmc_get_dma_dir(data));
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}
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static int sdmmc_idma_setup(struct mmci_host *host)
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{
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struct sdmmc_idma *idma;
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struct device *dev = mmc_dev(host->mmc);
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idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
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dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
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if (!idma || !dev->dma_parms)
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return -ENOMEM;
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host->dma_priv = idma;
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if (host->variant->dma_lli) {
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idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
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&idma->sg_dma, GFP_KERNEL);
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if (!idma->sg_cpu) {
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dev_err(dev, "Failed to alloc IDMA descriptor\n");
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return -ENOMEM;
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}
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host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
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sizeof(struct sdmmc_lli_desc);
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host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
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} else {
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host->mmc->max_segs = 1;
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host->mmc->max_seg_size = host->mmc->max_req_size;
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}
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dma_set_max_seg_size(dev, host->mmc->max_seg_size);
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return 0;
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}
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static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
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{
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struct sdmmc_idma *idma = host->dma_priv;
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struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
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struct mmc_data *data = host->data;
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struct scatterlist *sg;
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int i;
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if (!host->variant->dma_lli || data->sg_len == 1) {
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writel_relaxed(sg_dma_address(data->sg),
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host->base + MMCI_STM32_IDMABASE0R);
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writel_relaxed(MMCI_STM32_IDMAEN,
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host->base + MMCI_STM32_IDMACTRLR);
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return 0;
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}
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for_each_sg(data->sg, sg, data->sg_len, i) {
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desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
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desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
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| MMCI_STM32_ABR;
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desc[i].idmabase = sg_dma_address(sg);
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desc[i].idmasize = sg_dma_len(sg);
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}
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/* notice the end of link list */
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desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
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dma_wmb();
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writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
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writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
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writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
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writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
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writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
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host->base + MMCI_STM32_IDMACTRLR);
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return 0;
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}
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static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
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{
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writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
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if (!data->host_cookie)
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sdmmc_idma_unprep_data(host, data, 0);
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}
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static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
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{
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unsigned int clk = 0, ddr = 0;
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if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
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host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
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ddr = MCI_STM32_CLK_DDR;
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/*
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* cclk = mclk / (2 * clkdiv)
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* clkdiv 0 => bypass
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* in ddr mode bypass is not possible
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*/
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if (desired) {
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if (desired >= host->mclk && !ddr) {
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host->cclk = host->mclk;
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} else {
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clk = DIV_ROUND_UP(host->mclk, 2 * desired);
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if (clk > MCI_STM32_CLK_CLKDIV_MSK)
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clk = MCI_STM32_CLK_CLKDIV_MSK;
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host->cclk = host->mclk / (2 * clk);
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}
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} else {
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/*
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* while power-on phase the clock can't be define to 0,
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* Only power-off and power-cyc deactivate the clock.
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* if desired clock is 0, set max divider
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*/
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clk = MCI_STM32_CLK_CLKDIV_MSK;
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host->cclk = host->mclk / (2 * clk);
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}
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/* Set actual clock for debug */
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if (host->mmc->ios.power_mode == MMC_POWER_ON)
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host->mmc->actual_clock = host->cclk;
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else
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host->mmc->actual_clock = 0;
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if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
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clk |= MCI_STM32_CLK_WIDEBUS_4;
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if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
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clk |= MCI_STM32_CLK_WIDEBUS_8;
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clk |= MCI_STM32_CLK_HWFCEN;
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clk |= host->clk_reg_add;
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clk |= ddr;
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/*
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* SDMMC_FBCK is selected when an external Delay Block is needed
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* with SDR104.
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*/
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if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
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clk |= MCI_STM32_CLK_BUSSPEED;
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if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
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clk &= ~MCI_STM32_CLK_SEL_MSK;
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clk |= MCI_STM32_CLK_SELFBCK;
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}
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}
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mmci_write_clkreg(host, clk);
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}
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static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb)
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{
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if (!dlyb || !dlyb->base)
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return;
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/* Output clock = Input clock */
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writel_relaxed(0, dlyb->base + DLYB_CR);
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}
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static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
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{
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struct mmc_ios ios = host->mmc->ios;
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struct sdmmc_dlyb *dlyb = host->variant_priv;
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/* adds OF options */
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pwr = host->pwr_reg_add;
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sdmmc_dlyb_input_ck(dlyb);
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if (ios.power_mode == MMC_POWER_OFF) {
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/* Only a reset could power-off sdmmc */
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reset_control_assert(host->rst);
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udelay(2);
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reset_control_deassert(host->rst);
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/*
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* Set the SDMMC in Power-cycle state.
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* This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
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* are driven low, to prevent the Card from being supplied
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* through the signal lines.
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*/
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mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
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} else if (ios.power_mode == MMC_POWER_ON) {
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/*
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* After power-off (reset): the irq mask defined in probe
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* functionis lost
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* ault irq mask (probe) must be activated
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*/
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writel(MCI_IRQENABLE | host->variant->start_err,
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host->base + MMCIMASK0);
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/* preserves voltage switch bits */
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pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
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MCI_STM32_VSWITCH);
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/*
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* After a power-cycle state, we must set the SDMMC in
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* Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
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* driven high. Then we can set the SDMMC to Power-on state
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*/
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mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
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mdelay(1);
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mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
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}
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}
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static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
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{
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u32 datactrl;
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datactrl = mmci_dctrl_blksz(host);
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if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
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host->data->blocks == 1)
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datactrl |= MCI_DPSM_STM32_MODE_SDIO;
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else if (host->data->stop && !host->mrq->sbc)
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datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
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else
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datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
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return datactrl;
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}
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bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
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{
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void __iomem *base = host->base;
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u32 busy_d0, busy_d0end, mask;
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mask = readl_relaxed(base + MMCIMASK0);
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busy_d0end = readl_relaxed(base + MMCISTATUS) & MCI_STM32_BUSYD0END;
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busy_d0 = readl_relaxed(base + MMCISTATUS) & MCI_STM32_BUSYD0;
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/* complete if there is an error or busy_d0end */
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if ((status & err_msk) || busy_d0end)
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goto complete;
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/*
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* On response the busy signaling is reflected in the BUSYD0 flag.
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* if busy_d0 is in-progress we must activate busyd0end interrupt
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* to wait this completion. Else this request has no busy step.
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*/
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if (busy_d0) {
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if (!host->busy_status) {
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writel_relaxed(mask | host->variant->busy_detect_mask,
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base + MMCIMASK0);
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host->busy_status = status &
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||
|
|
(MCI_CMDSENT | MCI_CMDRESPEND);
|
||
|
|
}
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
complete:
|
||
|
|
writel_relaxed(mask & ~host->variant->busy_detect_mask,
|
||
|
|
base + MMCIMASK0);
|
||
|
|
writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
|
||
|
|
host->busy_status = 0;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb,
|
||
|
|
int unit, int phase, bool sampler)
|
||
|
|
{
|
||
|
|
u32 cfgr;
|
||
|
|
|
||
|
|
writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
|
||
|
|
|
||
|
|
cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
|
||
|
|
FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
|
||
|
|
writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
|
||
|
|
|
||
|
|
if (!sampler)
|
||
|
|
writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
|
||
|
|
{
|
||
|
|
struct sdmmc_dlyb *dlyb = host->variant_priv;
|
||
|
|
u32 cfgr;
|
||
|
|
int i, lng, ret;
|
||
|
|
|
||
|
|
for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
|
||
|
|
sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true);
|
||
|
|
|
||
|
|
ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
|
||
|
|
(cfgr & DLYB_CFGR_LNGF),
|
||
|
|
1, 1000);
|
||
|
|
if (ret) {
|
||
|
|
dev_warn(mmc_dev(host->mmc),
|
||
|
|
"delay line cfg timeout unit:%d cfgr:%d\n",
|
||
|
|
i, cfgr);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
|
||
|
|
if (lng < (BIT(11) | BIT(10)) && (lng & ~BIT(11)) > 0)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (i > DLYB_CFGR_UNIT_MAX)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
dlyb->unit = i;
|
||
|
|
dlyb->max = __fls(lng & ~BIT(11));
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
|
||
|
|
{
|
||
|
|
struct sdmmc_dlyb *dlyb = host->variant_priv;
|
||
|
|
int cur_len = 0, max_len = 0, end_of_len = 0;
|
||
|
|
int phase;
|
||
|
|
|
||
|
|
for (phase = 0; phase <= dlyb->max; phase++) {
|
||
|
|
sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
|
||
|
|
|
||
|
|
if (mmc_send_tuning(host->mmc, opcode, NULL)) {
|
||
|
|
cur_len = 0;
|
||
|
|
} else {
|
||
|
|
cur_len++;
|
||
|
|
if (cur_len > max_len) {
|
||
|
|
max_len = cur_len;
|
||
|
|
end_of_len = phase;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!max_len) {
|
||
|
|
dev_err(mmc_dev(host->mmc), "no tuning point found\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
writel_relaxed(0, dlyb->base + DLYB_CR);
|
||
|
|
|
||
|
|
phase = end_of_len - max_len / 2;
|
||
|
|
sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
|
||
|
|
|
||
|
|
dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
|
||
|
|
dlyb->unit, dlyb->max, phase);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
|
||
|
|
{
|
||
|
|
struct mmci_host *host = mmc_priv(mmc);
|
||
|
|
struct sdmmc_dlyb *dlyb = host->variant_priv;
|
||
|
|
|
||
|
|
if (!dlyb || !dlyb->base)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (sdmmc_dlyb_lng_tuning(host))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return sdmmc_dlyb_phase_tuning(host, opcode);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void sdmmc_prep_vswitch(struct mmci_host *host)
|
||
|
|
{
|
||
|
|
/* clear the voltage switch completion flag */
|
||
|
|
writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
|
||
|
|
/* enable Voltage switch procedure */
|
||
|
|
mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int sdmmc_vswitch(struct mmci_host *host, struct mmc_ios *ios)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
u32 status;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
|
||
|
|
spin_lock_irqsave(&host->lock, flags);
|
||
|
|
mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
|
||
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
||
|
|
|
||
|
|
/* wait voltage switch completion while 10ms */
|
||
|
|
ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
|
||
|
|
status,
|
||
|
|
(status & MCI_STM32_VSWEND),
|
||
|
|
10, 10000);
|
||
|
|
|
||
|
|
writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
|
||
|
|
host->base + MMCICLEAR);
|
||
|
|
|
||
|
|
spin_lock_irqsave(&host->lock, flags);
|
||
|
|
mmci_write_pwrreg(host, host->pwr_reg &
|
||
|
|
~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
|
||
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct mmci_host_ops sdmmc_variant_ops = {
|
||
|
|
.validate_data = sdmmc_idma_validate_data,
|
||
|
|
.prep_data = sdmmc_idma_prep_data,
|
||
|
|
.unprep_data = sdmmc_idma_unprep_data,
|
||
|
|
.get_datactrl_cfg = sdmmc_get_dctrl_cfg,
|
||
|
|
.dma_setup = sdmmc_idma_setup,
|
||
|
|
.dma_start = sdmmc_idma_start,
|
||
|
|
.dma_finalize = sdmmc_idma_finalize,
|
||
|
|
.set_clkreg = mmci_sdmmc_set_clkreg,
|
||
|
|
.set_pwrreg = mmci_sdmmc_set_pwrreg,
|
||
|
|
.busy_complete = sdmmc_busy_complete,
|
||
|
|
.prep_volt_switch = sdmmc_prep_vswitch,
|
||
|
|
.volt_switch = sdmmc_vswitch,
|
||
|
|
};
|
||
|
|
|
||
|
|
void sdmmc_variant_init(struct mmci_host *host)
|
||
|
|
{
|
||
|
|
struct device_node *np = host->mmc->parent->of_node;
|
||
|
|
void __iomem *base_dlyb;
|
||
|
|
struct sdmmc_dlyb *dlyb;
|
||
|
|
|
||
|
|
host->ops = &sdmmc_variant_ops;
|
||
|
|
|
||
|
|
base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
|
||
|
|
if (IS_ERR(base_dlyb))
|
||
|
|
return;
|
||
|
|
|
||
|
|
dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
|
||
|
|
if (!dlyb)
|
||
|
|
return;
|
||
|
|
|
||
|
|
dlyb->base = base_dlyb;
|
||
|
|
host->variant_priv = dlyb;
|
||
|
|
host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
|
||
|
|
}
|