246 lines
6.2 KiB
C
246 lines
6.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Microchip Image Sensor Controller (ISC) driver header file
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*
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* Copyright (C) 2016-2019 Microchip Technology, Inc.
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*
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* Author: Songjun Wu
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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*
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*/
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#ifndef _ATMEL_ISC_H_
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#define ISC_MAX_SUPPORT_WIDTH 2592
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#define ISC_MAX_SUPPORT_HEIGHT 1944
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#define ISC_CLK_MAX_DIV 255
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enum isc_clk_id {
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ISC_ISPCK = 0,
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ISC_MCK = 1,
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};
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struct isc_clk {
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struct clk_hw hw;
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struct clk *clk;
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struct regmap *regmap;
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spinlock_t lock; /* serialize access to clock registers */
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u8 id;
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u8 parent_id;
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u32 div;
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struct device *dev;
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};
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#define to_isc_clk(v) container_of(v, struct isc_clk, hw)
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struct isc_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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};
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struct isc_subdev_entity {
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struct v4l2_subdev *sd;
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struct v4l2_async_subdev *asd;
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struct v4l2_async_notifier notifier;
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u32 pfe_cfg0;
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struct list_head list;
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};
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/*
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* struct isc_format - ISC media bus format information
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This structure represents the interface between the ISC
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and the sensor. It's the input format received by
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the ISC.
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* @fourcc: Fourcc code for this format
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* @mbus_code: V4L2 media bus format code.
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* @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer.
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this is either BGBG, RGRG, etc.
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* @pfe_cfg0_bps: Number of hardware data lines connected to the ISC
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*/
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struct isc_format {
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u32 fourcc;
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u32 mbus_code;
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u32 cfa_baycfg;
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bool sd_support;
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u32 pfe_cfg0_bps;
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};
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/* Pipeline bitmap */
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#define WB_ENABLE BIT(0)
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#define CFA_ENABLE BIT(1)
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#define CC_ENABLE BIT(2)
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#define GAM_ENABLE BIT(3)
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#define GAM_BENABLE BIT(4)
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#define GAM_GENABLE BIT(5)
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#define GAM_RENABLE BIT(6)
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#define CSC_ENABLE BIT(7)
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#define CBC_ENABLE BIT(8)
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#define SUB422_ENABLE BIT(9)
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#define SUB420_ENABLE BIT(10)
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#define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
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/*
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* struct fmt_config - ISC format configuration and internal pipeline
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This structure represents the internal configuration
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of the ISC.
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It also holds the format that ISC will present to v4l2.
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* @sd_format: Pointer to an isc_format struct that holds the sensor
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configuration.
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* @fourcc: Fourcc code for this format.
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* @bpp: Bytes per pixel in the current format.
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* @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging)
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* @dcfg_imode: Configuration of the input of the DMA module
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* @dctrl_dview: Configuration of the output of the DMA module
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* @bits_pipeline: Configuration of the pipeline, which modules are enabled
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*/
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struct fmt_config {
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struct isc_format *sd_format;
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u32 fourcc;
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u8 bpp;
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u32 rlp_cfg_mode;
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u32 dcfg_imode;
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u32 dctrl_dview;
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u32 bits_pipeline;
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};
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#define HIST_ENTRIES 512
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#define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1)
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enum{
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HIST_INIT = 0,
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HIST_ENABLED,
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HIST_DISABLED,
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};
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struct isc_ctrls {
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struct v4l2_ctrl_handler handler;
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u32 brightness;
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u32 contrast;
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u8 gamma_index;
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#define ISC_WB_NONE 0
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#define ISC_WB_AUTO 1
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#define ISC_WB_ONETIME 2
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u8 awb;
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/* one for each component : GR, R, GB, B */
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u32 gain[HIST_BAYER];
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u32 offset[HIST_BAYER];
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u32 hist_entry[HIST_ENTRIES];
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u32 hist_count[HIST_BAYER];
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u8 hist_id;
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u8 hist_stat;
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#define HIST_MIN_INDEX 0
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#define HIST_MAX_INDEX 1
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u32 hist_minmax[HIST_BAYER][2];
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};
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#define ISC_PIPE_LINE_NODE_NUM 11
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/*
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* struct isc_device - ISC device driver data/config struct
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* @regmap: Register map
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* @hclock: Hclock clock input (refer datasheet)
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* @ispck: iscpck clock (refer datasheet)
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* @isc_clks: ISC clocks
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*
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* @dev: Registered device driver
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* @v4l2_dev: v4l2 registered device
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* @video_dev: registered video device
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*
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* @vb2_vidq: video buffer 2 video queue
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* @dma_queue_lock: lock to serialize the dma buffer queue
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* @dma_queue: the queue for dma buffers
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* @cur_frm: current isc frame/buffer
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* @sequence: current frame number
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* @stop: true if isc is not streaming, false if streaming
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* @comp: completion reference that signals frame completion
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*
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* @fmt: current v42l format
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* @user_formats: list of formats that are supported and agreed with sd
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* @num_user_formats: how many formats are in user_formats
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*
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* @config: current ISC format configuration
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* @try_config: the current ISC try format , not yet activated
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*
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* @ctrls: holds information about ISC controls
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* @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button
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* @awb_work: workqueue reference for autowhitebalance histogram
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* analysis
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*
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* @lock: lock for serializing userspace file operations
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* with ISC operations
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* @awb_lock: lock for serializing awb work queue operations
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* with DMA/buffer operations
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*
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* @pipeline: configuration of the ISC pipeline
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*
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* @current_subdev: current subdevice: the sensor
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* @subdev_entities: list of subdevice entitites
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*/
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struct isc_device {
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struct regmap *regmap;
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struct clk *hclock;
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struct clk *ispck;
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struct isc_clk isc_clks[2];
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struct device *dev;
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struct v4l2_device v4l2_dev;
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struct video_device video_dev;
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struct vb2_queue vb2_vidq;
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spinlock_t dma_queue_lock; /* serialize access to dma queue */
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struct list_head dma_queue;
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struct isc_buffer *cur_frm;
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unsigned int sequence;
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bool stop;
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struct completion comp;
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struct v4l2_format fmt;
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struct isc_format **user_formats;
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unsigned int num_user_formats;
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struct fmt_config config;
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struct fmt_config try_config;
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struct isc_ctrls ctrls;
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struct v4l2_ctrl *do_wb_ctrl;
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struct work_struct awb_work;
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struct mutex lock; /* serialize access to file operations */
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spinlock_t awb_lock; /* serialize access to DMA buffers from awb work queue */
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struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM];
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struct isc_subdev_entity *current_subdev;
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struct list_head subdev_entities;
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};
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#define GAMMA_MAX 2
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#define GAMMA_ENTRIES 64
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#define ATMEL_ISC_NAME "atmel-isc"
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extern struct isc_format formats_list[];
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extern const struct isc_format controller_formats[];
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extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES];
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extern const struct regmap_config isc_regmap_config;
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extern const struct v4l2_async_notifier_operations isc_async_ops;
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irqreturn_t isc_interrupt(int irq, void *dev_id);
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int isc_pipeline_init(struct isc_device *isc);
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int isc_clk_init(struct isc_device *isc);
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void isc_subdev_cleanup(struct isc_device *isc);
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void isc_clk_cleanup(struct isc_device *isc);
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#endif
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