446 lines
14 KiB
C
446 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Driver for Analog Devices ADV748X video decoder and HDMI receiver
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*
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* Copyright (C) 2017 Renesas Electronics Corp.
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*
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* Authors:
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* Koji Matsuoka <koji.matsuoka.xm@renesas.com>
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* Niklas Söderlund <niklas.soderlund@ragnatech.se>
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* Kieran Bingham <kieran.bingham@ideasonboard.com>
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*
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* The ADV748x range of receivers have the following configurations:
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*
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* Analog HDMI MHL 4-Lane 1-Lane
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* In In CSI CSI
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* ADV7480 X X X
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* ADV7481 X X X X X
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* ADV7482 X X X X
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*/
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#include <linux/i2c.h>
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#ifndef _ADV748X_H_
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#define _ADV748X_H_
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enum adv748x_page {
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ADV748X_PAGE_IO,
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ADV748X_PAGE_DPLL,
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ADV748X_PAGE_CP,
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ADV748X_PAGE_HDMI,
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ADV748X_PAGE_EDID,
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ADV748X_PAGE_REPEATER,
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ADV748X_PAGE_INFOFRAME,
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ADV748X_PAGE_CBUS,
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ADV748X_PAGE_CEC,
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ADV748X_PAGE_SDP,
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ADV748X_PAGE_TXB,
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ADV748X_PAGE_TXA,
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ADV748X_PAGE_MAX,
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/* Fake pages for register sequences */
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ADV748X_PAGE_EOR, /* End Mark */
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};
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/**
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* enum adv748x_ports - Device tree port number definitions
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*
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* The ADV748X ports define the mapping between subdevices
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* and the device tree specification
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*/
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enum adv748x_ports {
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ADV748X_PORT_AIN0 = 0,
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ADV748X_PORT_AIN1 = 1,
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ADV748X_PORT_AIN2 = 2,
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ADV748X_PORT_AIN3 = 3,
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ADV748X_PORT_AIN4 = 4,
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ADV748X_PORT_AIN5 = 5,
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ADV748X_PORT_AIN6 = 6,
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ADV748X_PORT_AIN7 = 7,
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ADV748X_PORT_HDMI = 8,
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ADV748X_PORT_TTL = 9,
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ADV748X_PORT_TXA = 10,
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ADV748X_PORT_TXB = 11,
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ADV748X_PORT_MAX = 12,
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};
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enum adv748x_csi2_pads {
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ADV748X_CSI2_SINK,
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ADV748X_CSI2_SOURCE,
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ADV748X_CSI2_NR_PADS,
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};
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/* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
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#define ADV748X_CSI2_MAX_SUBDEVS 2
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struct adv748x_csi2 {
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struct adv748x_state *state;
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struct v4l2_mbus_framefmt format;
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unsigned int page;
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unsigned int port;
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unsigned int num_lanes;
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struct media_pad pads[ADV748X_CSI2_NR_PADS];
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struct v4l2_ctrl_handler ctrl_hdl;
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struct v4l2_ctrl *pixel_rate;
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struct v4l2_subdev *src;
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struct v4l2_subdev sd;
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};
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#define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
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#define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
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#define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)
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#define is_txa(_tx) ((_tx) == &(_tx)->state->txa)
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#define is_txb(_tx) ((_tx) == &(_tx)->state->txb)
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#define is_tx(_tx) (is_txa(_tx) || is_txb(_tx))
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#define is_afe_enabled(_state) \
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((_state)->endpoints[ADV748X_PORT_AIN0] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN1] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN2] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN3] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN4] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN5] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN6] != NULL || \
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(_state)->endpoints[ADV748X_PORT_AIN7] != NULL)
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#define is_hdmi_enabled(_state) ((_state)->endpoints[ADV748X_PORT_HDMI] != NULL)
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enum adv748x_hdmi_pads {
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ADV748X_HDMI_SINK,
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ADV748X_HDMI_SOURCE,
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ADV748X_HDMI_NR_PADS,
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};
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struct adv748x_hdmi {
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struct media_pad pads[ADV748X_HDMI_NR_PADS];
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struct v4l2_ctrl_handler ctrl_hdl;
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struct v4l2_subdev sd;
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struct v4l2_mbus_framefmt format;
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struct v4l2_dv_timings timings;
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struct v4l2_fract aspect_ratio;
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struct adv748x_csi2 *tx;
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struct {
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u8 edid[512];
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u32 present;
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unsigned int blocks;
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} edid;
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};
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#define adv748x_ctrl_to_hdmi(ctrl) \
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container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
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#define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
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enum adv748x_afe_pads {
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ADV748X_AFE_SINK_AIN0,
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ADV748X_AFE_SINK_AIN1,
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ADV748X_AFE_SINK_AIN2,
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ADV748X_AFE_SINK_AIN3,
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ADV748X_AFE_SINK_AIN4,
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ADV748X_AFE_SINK_AIN5,
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ADV748X_AFE_SINK_AIN6,
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ADV748X_AFE_SINK_AIN7,
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ADV748X_AFE_SOURCE,
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ADV748X_AFE_NR_PADS,
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};
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struct adv748x_afe {
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struct media_pad pads[ADV748X_AFE_NR_PADS];
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struct v4l2_ctrl_handler ctrl_hdl;
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struct v4l2_subdev sd;
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struct v4l2_mbus_framefmt format;
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struct adv748x_csi2 *tx;
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bool streaming;
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v4l2_std_id curr_norm;
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unsigned int input;
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};
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#define adv748x_ctrl_to_afe(ctrl) \
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container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
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#define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
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/**
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* struct adv748x_state - State of ADV748X
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* @dev: (OF) device
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* @client: I2C client
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* @mutex: protect global state
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*
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* @endpoints: parsed device node endpoints for each port
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*
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* @i2c_addresses I2C Page addresses
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* @i2c_clients I2C clients for the page accesses
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* @regmap regmap configuration pages.
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*
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* @hdmi: state of HDMI receiver context
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* @afe: state of AFE receiver context
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* @txa: state of TXA transmitter context
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* @txb: state of TXB transmitter context
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*/
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struct adv748x_state {
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struct device *dev;
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struct i2c_client *client;
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struct mutex mutex;
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struct device_node *endpoints[ADV748X_PORT_MAX];
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struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
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struct regmap *regmap[ADV748X_PAGE_MAX];
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struct adv748x_hdmi hdmi;
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struct adv748x_afe afe;
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struct adv748x_csi2 txa;
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struct adv748x_csi2 txb;
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};
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#define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
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#define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
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#define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
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#define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
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#define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
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/* Register Mappings */
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/* IO Map */
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#define ADV748X_IO_PD 0x00 /* power down controls */
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#define ADV748X_IO_PD_RX_EN BIT(6)
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#define ADV748X_IO_REG_01 0x01 /* pwrdn{2}b, prog_xtal_freq */
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#define ADV748X_IO_REG_01_PWRDN_MASK (BIT(7) | BIT(6))
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#define ADV748X_IO_REG_01_PWRDN2B BIT(7) /* CEC Wakeup Support */
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#define ADV748X_IO_REG_01_PWRDNB BIT(6) /* CEC Wakeup Support */
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#define ADV748X_IO_REG_04 0x04
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#define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */
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#define ADV748X_IO_DATAPATH 0x03 /* datapath cntrl */
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#define ADV748X_IO_DATAPATH_VFREQ_M 0x70
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#define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
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#define ADV748X_IO_VID_STD 0x05
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#define ADV748X_IO_10 0x10 /* io_reg_10 */
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#define ADV748X_IO_10_CSI4_EN BIT(7)
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#define ADV748X_IO_10_CSI1_EN BIT(6)
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#define ADV748X_IO_10_PIX_OUT_EN BIT(5)
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#define ADV748X_IO_10_CSI4_IN_SEL_AFE BIT(3)
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#define ADV748X_IO_CHIP_REV_ID_1 0xdf
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#define ADV748X_IO_CHIP_REV_ID_2 0xe0
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#define ADV748X_IO_REG_F2 0xf2
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#define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0)
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/* For PAGE slave address offsets */
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#define ADV748X_IO_SLAVE_ADDR_BASE 0xf2
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/*
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* The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80 and
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* 0xff as examples for performing a software reset.
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*/
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#define ADV748X_IO_REG_FF 0xff
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#define ADV748X_IO_REG_FF_MAIN_RESET 0xff
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/* HDMI RX Map */
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#define ADV748X_HDMI_LW1 0x07 /* line width_1 */
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#define ADV748X_HDMI_LW1_VERT_FILTER BIT(7)
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#define ADV748X_HDMI_LW1_DE_REGEN BIT(5)
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#define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff
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#define ADV748X_HDMI_F0H1 0x09 /* field0 height_1 */
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#define ADV748X_HDMI_F0H1_HEIGHT_MASK 0x1fff
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#define ADV748X_HDMI_F1H1 0x0b /* field1 height_1 */
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#define ADV748X_HDMI_F1H1_INTERLACED BIT(5)
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#define ADV748X_HDMI_HFRONT_PORCH 0x20 /* hsync_front_porch_1 */
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#define ADV748X_HDMI_HFRONT_PORCH_MASK 0x1fff
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#define ADV748X_HDMI_HSYNC_WIDTH 0x22 /* hsync_pulse_width_1 */
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#define ADV748X_HDMI_HSYNC_WIDTH_MASK 0x1fff
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#define ADV748X_HDMI_HBACK_PORCH 0x24 /* hsync_back_porch_1 */
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#define ADV748X_HDMI_HBACK_PORCH_MASK 0x1fff
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#define ADV748X_HDMI_VFRONT_PORCH 0x2a /* field0_vs_front_porch_1 */
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#define ADV748X_HDMI_VFRONT_PORCH_MASK 0x3fff
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#define ADV748X_HDMI_VSYNC_WIDTH 0x2e /* field0_vs_pulse_width_1 */
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#define ADV748X_HDMI_VSYNC_WIDTH_MASK 0x3fff
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#define ADV748X_HDMI_VBACK_PORCH 0x32 /* field0_vs_back_porch_1 */
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#define ADV748X_HDMI_VBACK_PORCH_MASK 0x3fff
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#define ADV748X_HDMI_TMDS_1 0x51 /* hdmi_reg_51 */
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#define ADV748X_HDMI_TMDS_2 0x52 /* hdmi_reg_52 */
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/* HDMI RX Repeater Map */
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#define ADV748X_REPEATER_EDID_SZ 0x70 /* primary_edid_size */
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#define ADV748X_REPEATER_EDID_SZ_SHIFT 4
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#define ADV748X_REPEATER_EDID_CTL 0x74 /* hdcp edid controls */
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#define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */
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/* SDP Main Map */
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#define ADV748X_SDP_INSEL 0x00 /* user_map_rw_reg_00 */
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#define ADV748X_SDP_VID_SEL 0x02 /* user_map_rw_reg_02 */
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#define ADV748X_SDP_VID_SEL_MASK 0xf0
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#define ADV748X_SDP_VID_SEL_SHIFT 4
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/* Contrast - Unsigned*/
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#define ADV748X_SDP_CON 0x08 /* user_map_rw_reg_08 */
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#define ADV748X_SDP_CON_MIN 0
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#define ADV748X_SDP_CON_DEF 128
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#define ADV748X_SDP_CON_MAX 255
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/* Brightness - Signed */
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#define ADV748X_SDP_BRI 0x0a /* user_map_rw_reg_0a */
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#define ADV748X_SDP_BRI_MIN -128
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#define ADV748X_SDP_BRI_DEF 0
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#define ADV748X_SDP_BRI_MAX 127
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/* Hue - Signed, inverted*/
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#define ADV748X_SDP_HUE 0x0b /* user_map_rw_reg_0b */
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#define ADV748X_SDP_HUE_MIN -127
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#define ADV748X_SDP_HUE_DEF 0
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#define ADV748X_SDP_HUE_MAX 128
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/* Test Patterns / Default Values */
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#define ADV748X_SDP_DEF 0x0c /* user_map_rw_reg_0c */
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#define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */
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#define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1) /* Free run when no signal */
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#define ADV748X_SDP_MAP_SEL 0x0e /* user_map_rw_reg_0e */
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#define ADV748X_SDP_MAP_SEL_RO_MAIN 1
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/* Free run pattern select */
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#define ADV748X_SDP_FRP 0x14
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#define ADV748X_SDP_FRP_MASK GENMASK(3, 1)
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/* Saturation */
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#define ADV748X_SDP_SD_SAT_U 0xe3 /* user_map_rw_reg_e3 */
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#define ADV748X_SDP_SD_SAT_V 0xe4 /* user_map_rw_reg_e4 */
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#define ADV748X_SDP_SAT_MIN 0
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#define ADV748X_SDP_SAT_DEF 128
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#define ADV748X_SDP_SAT_MAX 255
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/* SDP RO Main Map */
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#define ADV748X_SDP_RO_10 0x10
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#define ADV748X_SDP_RO_10_IN_LOCK BIT(0)
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/* CP Map */
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#define ADV748X_CP_PAT_GEN 0x37 /* int_pat_gen_1 */
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#define ADV748X_CP_PAT_GEN_EN BIT(7)
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/* Contrast Control - Unsigned */
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#define ADV748X_CP_CON 0x3a /* contrast_cntrl */
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#define ADV748X_CP_CON_MIN 0 /* Minimum contrast */
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#define ADV748X_CP_CON_DEF 128 /* Default */
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#define ADV748X_CP_CON_MAX 255 /* Maximum contrast */
|
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/* Saturation Control - Unsigned */
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#define ADV748X_CP_SAT 0x3b /* saturation_cntrl */
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#define ADV748X_CP_SAT_MIN 0 /* Minimum saturation */
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#define ADV748X_CP_SAT_DEF 128 /* Default */
|
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#define ADV748X_CP_SAT_MAX 255 /* Maximum saturation */
|
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|
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/* Brightness Control - Signed */
|
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#define ADV748X_CP_BRI 0x3c /* brightness_cntrl */
|
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#define ADV748X_CP_BRI_MIN -128 /* Luma is -512d */
|
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#define ADV748X_CP_BRI_DEF 0 /* Luma is 0 */
|
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|
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#define ADV748X_CP_BRI_MAX 127 /* Luma is 508d */
|
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|
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|
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|
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/* Hue Control */
|
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|
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#define ADV748X_CP_HUE 0x3d /* hue_cntrl */
|
||
|
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#define ADV748X_CP_HUE_MIN 0 /* -90 degree */
|
||
|
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#define ADV748X_CP_HUE_DEF 0 /* -90 degree */
|
||
|
|
#define ADV748X_CP_HUE_MAX 255 /* +90 degree */
|
||
|
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|
||
|
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#define ADV748X_CP_VID_ADJ 0x3e /* vid_adj_0 */
|
||
|
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#define ADV748X_CP_VID_ADJ_ENABLE BIT(7) /* Enable colour controls */
|
||
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|
||
|
|
#define ADV748X_CP_DE_POS_HIGH 0x8b /* de_pos_adj_6 */
|
||
|
|
#define ADV748X_CP_DE_POS_HIGH_SET BIT(6)
|
||
|
|
#define ADV748X_CP_DE_POS_END_LOW 0x8c /* de_pos_adj_7 */
|
||
|
|
#define ADV748X_CP_DE_POS_START_LOW 0x8d /* de_pos_adj_8 */
|
||
|
|
|
||
|
|
#define ADV748X_CP_VID_ADJ_2 0x91
|
||
|
|
#define ADV748X_CP_VID_ADJ_2_INTERLACED BIT(6)
|
||
|
|
#define ADV748X_CP_VID_ADJ_2_INTERLACED_3D BIT(4)
|
||
|
|
|
||
|
|
#define ADV748X_CP_CLMP_POS 0xc9 /* clmp_pos_cntrl_4 */
|
||
|
|
#define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */
|
||
|
|
|
||
|
|
/* CSI : TXA/TXB Maps */
|
||
|
|
#define ADV748X_CSI_VC_REF 0x0d /* csi_tx_top_reg_0d */
|
||
|
|
#define ADV748X_CSI_VC_REF_SHIFT 6
|
||
|
|
|
||
|
|
#define ADV748X_CSI_FS_AS_LS 0x1e /* csi_tx_top_reg_1e */
|
||
|
|
#define ADV748X_CSI_FS_AS_LS_UNKNOWN BIT(6) /* Undocumented bit */
|
||
|
|
|
||
|
|
/* Register handling */
|
||
|
|
|
||
|
|
int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
|
||
|
|
int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
|
||
|
|
int adv748x_write_block(struct adv748x_state *state, int client_page,
|
||
|
|
unsigned int init_reg, const void *val,
|
||
|
|
size_t val_len);
|
||
|
|
|
||
|
|
#define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
|
||
|
|
#define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
|
||
|
|
#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))
|
||
|
|
|
||
|
|
#define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
|
||
|
|
#define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, (r)+1)) & (m))
|
||
|
|
#define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
|
||
|
|
|
||
|
|
#define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
|
||
|
|
#define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
|
||
|
|
|
||
|
|
#define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
|
||
|
|
#define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
|
||
|
|
#define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v))
|
||
|
|
|
||
|
|
#define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
|
||
|
|
#define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
|
||
|
|
#define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v))
|
||
|
|
|
||
|
|
#define tx_read(t, r) adv748x_read(t->state, t->page, r)
|
||
|
|
#define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
|
||
|
|
|
||
|
|
static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
|
||
|
|
{
|
||
|
|
pad = media_entity_remote_pad(pad);
|
||
|
|
if (!pad)
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
return media_entity_to_v4l2_subdev(pad->entity);
|
||
|
|
}
|
||
|
|
|
||
|
|
void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
|
||
|
|
const struct v4l2_subdev_ops *ops, u32 function,
|
||
|
|
const char *ident);
|
||
|
|
|
||
|
|
int adv748x_register_subdevs(struct adv748x_state *state,
|
||
|
|
struct v4l2_device *v4l2_dev);
|
||
|
|
|
||
|
|
int adv748x_tx_power(struct adv748x_csi2 *tx, bool on);
|
||
|
|
|
||
|
|
int adv748x_afe_init(struct adv748x_afe *afe);
|
||
|
|
void adv748x_afe_cleanup(struct adv748x_afe *afe);
|
||
|
|
|
||
|
|
int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
|
||
|
|
void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
|
||
|
|
int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
|
||
|
|
|
||
|
|
int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
|
||
|
|
void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
|
||
|
|
|
||
|
|
#endif /* _ADV748X_H_ */
|