43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header file for FPGA Management Engine (FME) Driver
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Wu Hao <hao.wu@intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#ifndef __DFL_FME_H
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#define __DFL_FME_H
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/**
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* struct dfl_fme - dfl fme private data
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*
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* @mgr: FME's FPGA manager platform device.
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* @region_list: linked list of FME's FPGA regions.
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* @bridge_list: linked list of FME's FPGA bridges.
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* @pdata: fme platform device's pdata.
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*/
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struct dfl_fme {
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struct platform_device *mgr;
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struct list_head region_list;
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struct list_head bridge_list;
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struct dfl_feature_platform_data *pdata;
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};
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extern const struct dfl_feature_ops fme_pr_mgmt_ops;
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extern const struct dfl_feature_id fme_pr_mgmt_id_table[];
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extern const struct dfl_feature_ops fme_global_err_ops;
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extern const struct dfl_feature_id fme_global_err_id_table[];
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extern const struct attribute_group fme_global_err_group;
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#endif /* __DFL_FME_H */
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