132 lines
2.8 KiB
C
132 lines
2.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Clocksource using the Low Power Timer found in the Low Power Controller (LPC)
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*
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* Copyright (C) 2015 STMicroelectronics – All Rights Reserved
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*
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* Author(s): Francesco Virlinzi <francesco.virlinzi@st.com>
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* Ajit Pal Singh <ajitpal.singh@st.com>
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include <dt-bindings/mfd/st-lpc.h>
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/* Low Power Timer */
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#define LPC_LPT_LSB_OFF 0x400
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#define LPC_LPT_MSB_OFF 0x404
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#define LPC_LPT_START_OFF 0x408
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static struct st_clksrc_ddata {
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struct clk *clk;
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void __iomem *base;
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} ddata;
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static void __init st_clksrc_reset(void)
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{
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writel_relaxed(0, ddata.base + LPC_LPT_START_OFF);
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writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF);
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writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF);
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writel_relaxed(1, ddata.base + LPC_LPT_START_OFF);
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}
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static u64 notrace st_clksrc_sched_clock_read(void)
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{
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return (u64)readl_relaxed(ddata.base + LPC_LPT_LSB_OFF);
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}
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static int __init st_clksrc_init(void)
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{
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unsigned long rate;
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int ret;
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st_clksrc_reset();
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rate = clk_get_rate(ddata.clk);
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sched_clock_register(st_clksrc_sched_clock_read, 32, rate);
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ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF,
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"clksrc-st-lpc", rate, 300, 32,
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clocksource_mmio_readl_up);
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if (ret) {
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pr_err("clksrc-st-lpc: Failed to register clocksource\n");
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return ret;
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}
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return 0;
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}
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static int __init st_clksrc_setup_clk(struct device_node *np)
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{
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struct clk *clk;
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("clksrc-st-lpc: Failed to get LPC clock\n");
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return PTR_ERR(clk);
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}
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if (clk_prepare_enable(clk)) {
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pr_err("clksrc-st-lpc: Failed to enable LPC clock\n");
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return -EINVAL;
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}
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if (!clk_get_rate(clk)) {
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pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n");
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clk_disable_unprepare(clk);
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return -EINVAL;
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}
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ddata.clk = clk;
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return 0;
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}
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static int __init st_clksrc_of_register(struct device_node *np)
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{
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int ret;
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uint32_t mode;
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ret = of_property_read_u32(np, "st,lpc-mode", &mode);
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if (ret) {
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pr_err("clksrc-st-lpc: An LPC mode must be provided\n");
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return ret;
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}
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/* LPC can either run as a Clocksource or in RTC or WDT mode */
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if (mode != ST_LPC_MODE_CLKSRC)
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return 0;
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ddata.base = of_iomap(np, 0);
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if (!ddata.base) {
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pr_err("clksrc-st-lpc: Unable to map iomem\n");
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return -ENXIO;
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}
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ret = st_clksrc_setup_clk(np);
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if (ret) {
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iounmap(ddata.base);
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return ret;
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}
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ret = st_clksrc_init();
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if (ret) {
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clk_disable_unprepare(ddata.clk);
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clk_put(ddata.clk);
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iounmap(ddata.base);
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return ret;
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}
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pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n",
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clk_get_rate(ddata.clk));
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return ret;
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}
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TIMER_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);
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