407 lines
7.6 KiB
C
407 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2018 Andes Technology Corporation
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#include <asm/bitfield.h>
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#include <asm/uaccess.h>
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#include <asm/sfp-machine.h>
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#include <asm/fpuemu.h>
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#include <asm/nds32_fpu_inst.h>
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#define DPFROMREG(dp, x) (dp = (void *)((unsigned long *)fpu_reg + 2*x))
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#ifdef __NDS32_EL__
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#define SPFROMREG(sp, x)\
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((sp) = (void *)((unsigned long *)fpu_reg + (x^1)))
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#else
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#define SPFROMREG(sp, x) ((sp) = (void *)((unsigned long *)fpu_reg + x))
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#endif
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#define DEF3OP(name, p, f1, f2) \
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void fpemu_##name##p(void *ft, void *fa, void *fb) \
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{ \
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f1(fa, fa, fb); \
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f2(ft, ft, fa); \
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}
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#define DEF3OPNEG(name, p, f1, f2, f3) \
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void fpemu_##name##p(void *ft, void *fa, void *fb) \
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{ \
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f1(fa, fa, fb); \
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f2(ft, ft, fa); \
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f3(ft, ft); \
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}
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DEF3OP(fmadd, s, fmuls, fadds);
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DEF3OP(fmsub, s, fmuls, fsubs);
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DEF3OP(fmadd, d, fmuld, faddd);
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DEF3OP(fmsub, d, fmuld, fsubd);
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DEF3OPNEG(fnmadd, s, fmuls, fadds, fnegs);
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DEF3OPNEG(fnmsub, s, fmuls, fsubs, fnegs);
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DEF3OPNEG(fnmadd, d, fmuld, faddd, fnegd);
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DEF3OPNEG(fnmsub, d, fmuld, fsubd, fnegd);
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static const unsigned char cmptab[8] = {
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SF_CEQ,
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SF_CEQ,
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SF_CLT,
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SF_CLT,
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SF_CLT | SF_CEQ,
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SF_CLT | SF_CEQ,
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SF_CUN,
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SF_CUN
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};
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enum ARGTYPE {
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S1S = 1,
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S2S,
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S1D,
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CS,
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D1D,
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D2D,
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D1S,
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CD
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};
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union func_t {
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void (*t)(void *ft, void *fa, void *fb);
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void (*b)(void *ft, void *fa);
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};
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/*
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* Emulate a single FPU arithmetic instruction.
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*/
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static int fpu_emu(struct fpu_struct *fpu_reg, unsigned long insn)
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{
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int rfmt; /* resulting format */
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union func_t func;
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int ftype = 0;
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switch (rfmt = NDS32Insn_OPCODE_COP0(insn)) {
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case fs1_op:{
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switch (NDS32Insn_OPCODE_BIT69(insn)) {
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case fadds_op:
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func.t = fadds;
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ftype = S2S;
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break;
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case fsubs_op:
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func.t = fsubs;
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ftype = S2S;
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break;
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case fmadds_op:
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func.t = fpemu_fmadds;
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ftype = S2S;
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break;
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case fmsubs_op:
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func.t = fpemu_fmsubs;
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ftype = S2S;
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break;
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case fnmadds_op:
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func.t = fpemu_fnmadds;
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ftype = S2S;
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break;
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case fnmsubs_op:
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func.t = fpemu_fnmsubs;
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ftype = S2S;
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break;
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case fmuls_op:
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func.t = fmuls;
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ftype = S2S;
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break;
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case fdivs_op:
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func.t = fdivs;
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ftype = S2S;
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break;
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case fs1_f2op_op:
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switch (NDS32Insn_OPCODE_BIT1014(insn)) {
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case fs2d_op:
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func.b = fs2d;
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ftype = S1D;
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break;
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case fs2si_op:
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func.b = fs2si;
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ftype = S1S;
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break;
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case fs2si_z_op:
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func.b = fs2si_z;
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ftype = S1S;
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break;
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case fs2ui_op:
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func.b = fs2ui;
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ftype = S1S;
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break;
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case fs2ui_z_op:
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func.b = fs2ui_z;
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ftype = S1S;
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break;
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case fsi2s_op:
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func.b = fsi2s;
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ftype = S1S;
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break;
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case fui2s_op:
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func.b = fui2s;
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ftype = S1S;
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break;
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case fsqrts_op:
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func.b = fsqrts;
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ftype = S1S;
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break;
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default:
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return SIGILL;
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}
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break;
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default:
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return SIGILL;
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}
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break;
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}
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case fs2_op:
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switch (NDS32Insn_OPCODE_BIT69(insn)) {
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case fcmpeqs_op:
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case fcmpeqs_e_op:
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case fcmplts_op:
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case fcmplts_e_op:
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case fcmples_op:
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case fcmples_e_op:
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case fcmpuns_op:
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case fcmpuns_e_op:
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ftype = CS;
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break;
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default:
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return SIGILL;
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}
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break;
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case fd1_op:{
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switch (NDS32Insn_OPCODE_BIT69(insn)) {
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case faddd_op:
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func.t = faddd;
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ftype = D2D;
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break;
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case fsubd_op:
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func.t = fsubd;
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ftype = D2D;
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break;
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case fmaddd_op:
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func.t = fpemu_fmaddd;
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ftype = D2D;
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break;
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case fmsubd_op:
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func.t = fpemu_fmsubd;
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ftype = D2D;
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break;
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case fnmaddd_op:
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func.t = fpemu_fnmaddd;
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ftype = D2D;
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break;
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case fnmsubd_op:
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func.t = fpemu_fnmsubd;
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ftype = D2D;
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break;
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case fmuld_op:
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func.t = fmuld;
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ftype = D2D;
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break;
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case fdivd_op:
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func.t = fdivd;
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ftype = D2D;
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break;
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case fd1_f2op_op:
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switch (NDS32Insn_OPCODE_BIT1014(insn)) {
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case fd2s_op:
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func.b = fd2s;
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ftype = D1S;
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break;
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case fd2si_op:
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func.b = fd2si;
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ftype = D1S;
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break;
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case fd2si_z_op:
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func.b = fd2si_z;
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ftype = D1S;
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break;
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case fd2ui_op:
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func.b = fd2ui;
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ftype = D1S;
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break;
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case fd2ui_z_op:
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func.b = fd2ui_z;
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ftype = D1S;
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break;
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case fsi2d_op:
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func.b = fsi2d;
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ftype = D1S;
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break;
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case fui2d_op:
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func.b = fui2d;
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ftype = D1S;
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break;
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case fsqrtd_op:
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func.b = fsqrtd;
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ftype = D1D;
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break;
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default:
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return SIGILL;
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}
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break;
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default:
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return SIGILL;
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}
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break;
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}
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case fd2_op:
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switch (NDS32Insn_OPCODE_BIT69(insn)) {
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case fcmpeqd_op:
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case fcmpeqd_e_op:
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case fcmpltd_op:
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case fcmpltd_e_op:
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case fcmpled_op:
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case fcmpled_e_op:
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case fcmpund_op:
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case fcmpund_e_op:
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ftype = CD;
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break;
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default:
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return SIGILL;
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}
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break;
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default:
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return SIGILL;
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}
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switch (ftype) {
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case S1S:{
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void *ft, *fa;
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SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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func.b(ft, fa);
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break;
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}
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case S2S:{
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void *ft, *fa, *fb;
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SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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SPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
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func.t(ft, fa, fb);
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break;
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}
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case S1D:{
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void *ft, *fa;
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DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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func.b(ft, fa);
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break;
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}
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case CS:{
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unsigned int cmpop = NDS32Insn_OPCODE_BIT69(insn);
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void *ft, *fa, *fb;
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SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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SPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
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if (cmpop < 0x8) {
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cmpop = cmptab[cmpop];
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fcmps(ft, fa, fb, cmpop);
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} else
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return SIGILL;
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break;
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}
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case D1D:{
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void *ft, *fa;
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DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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func.b(ft, fa);
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break;
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}
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case D2D:{
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void *ft, *fa, *fb;
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DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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DPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
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func.t(ft, fa, fb);
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break;
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}
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case D1S:{
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void *ft, *fa;
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SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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func.b(ft, fa);
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break;
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}
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case CD:{
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unsigned int cmpop = NDS32Insn_OPCODE_BIT69(insn);
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void *ft, *fa, *fb;
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SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn));
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DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn));
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DPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn));
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if (cmpop < 0x8) {
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cmpop = cmptab[cmpop];
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fcmpd(ft, fa, fb, cmpop);
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} else
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return SIGILL;
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break;
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}
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default:
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return SIGILL;
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}
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/*
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* If an exception is required, generate a tidy SIGFPE exception.
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*/
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#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC)
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if (((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE_NO_UDF_IEXE)
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|| ((fpu_reg->fpcsr << 5) & (fpu_reg->UDF_IEX_trap))) {
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#else
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if ((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE) {
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#endif
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return SIGFPE;
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}
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return 0;
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}
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int do_fpuemu(struct pt_regs *regs, struct fpu_struct *fpu)
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{
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unsigned long insn = 0, addr = regs->ipc;
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unsigned long emulpc, contpc;
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unsigned char *pc = (void *)&insn;
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char c;
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int i = 0, ret;
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for (i = 0; i < 4; i++) {
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if (__get_user(c, (unsigned char *)addr++))
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return SIGBUS;
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*pc++ = c;
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}
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insn = be32_to_cpu(insn);
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|
|
emulpc = regs->ipc;
|
||
|
|
contpc = regs->ipc + 4;
|
||
|
|
|
||
|
|
if (NDS32Insn_OPCODE(insn) != cop0_op)
|
||
|
|
return SIGILL;
|
||
|
|
|
||
|
|
switch (NDS32Insn_OPCODE_COP0(insn)) {
|
||
|
|
case fs1_op:
|
||
|
|
case fs2_op:
|
||
|
|
case fd1_op:
|
||
|
|
case fd2_op:
|
||
|
|
{
|
||
|
|
/* a real fpu computation instruction */
|
||
|
|
ret = fpu_emu(fpu, insn);
|
||
|
|
if (!ret)
|
||
|
|
regs->ipc = contpc;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return SIGILL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|