159 lines
4.4 KiB
C
159 lines
4.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2005-2018 Andes Technology Corporation */
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#include <asm/bitfield.h>
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#define _FP_W_TYPE_SIZE 32
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#define _FP_W_TYPE unsigned long
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#define _FP_WS_TYPE signed long
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#define _FP_I_TYPE long
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#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
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#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
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#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
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#define _FP_MUL_MEAT_S(R, X, Y) \
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_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S, R, X, Y, umul_ppmm)
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#define _FP_MUL_MEAT_D(R, X, Y) \
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D, R, X, Y, umul_ppmm)
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#define _FP_MUL_MEAT_Q(R, X, Y) \
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_FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q, R, X, Y, umul_ppmm)
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#define _FP_MUL_MEAT_DW_S(R, X, Y) \
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_FP_MUL_MEAT_DW_1_wide(_FP_WFRACBITS_S, R, X, Y, umul_ppmm)
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#define _FP_MUL_MEAT_DW_D(R, X, Y) \
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_FP_MUL_MEAT_DW_2_wide(_FP_WFRACBITS_D, R, X, Y, umul_ppmm)
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#define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm(S, R, X, Y)
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#define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_2_udiv(D, R, X, Y)
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#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
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#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
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#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
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#define _FP_NANSIGN_S 0
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#define _FP_NANSIGN_D 0
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#define _FP_NANSIGN_Q 0
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#define _FP_KEEPNANFRACP 1
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#define _FP_QNANNEGATEDP 0
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
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&& !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) { \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R, Y); \
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} else { \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R, X); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#define __FPU_FPCSR (current->thread.fpu.fpcsr)
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/* Obtain the current rounding mode. */
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#define FP_ROUNDMODE \
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({ \
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__FPU_FPCSR & FPCSR_mskRM; \
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})
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#define FP_RND_NEAREST 0
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#define FP_RND_PINF 1
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#define FP_RND_MINF 2
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#define FP_RND_ZERO 3
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#define FP_EX_INVALID FPCSR_mskIVO
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#define FP_EX_DIVZERO FPCSR_mskDBZ
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#define FP_EX_OVERFLOW FPCSR_mskOVF
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#define FP_EX_UNDERFLOW FPCSR_mskUDF
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#define FP_EX_INEXACT FPCSR_mskIEX
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#define SF_CEQ 2
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#define SF_CLT 1
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#define SF_CGT 3
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#define SF_CUN 4
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#include <asm/byteorder.h>
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#ifdef __BIG_ENDIAN__
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#define __BYTE_ORDER __BIG_ENDIAN
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#define __LITTLE_ENDIAN 0
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#else
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#define __BYTE_ORDER __LITTLE_ENDIAN
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#define __BIG_ENDIAN 0
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#endif
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#define abort() do { } while (0)
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#define umul_ppmm(w1, w0, u, v) \
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do { \
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UWtype __x0, __x1, __x2, __x3; \
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UHWtype __ul, __vl, __uh, __vh; \
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\
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__ul = __ll_lowpart(u); \
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__uh = __ll_highpart(u); \
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__vl = __ll_lowpart(v); \
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__vh = __ll_highpart(v); \
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\
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__x0 = (UWtype) __ul * __vl; \
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__x1 = (UWtype) __ul * __vh; \
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__x2 = (UWtype) __uh * __vl; \
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__x3 = (UWtype) __uh * __vh; \
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\
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__x1 += __ll_highpart(__x0); \
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__x1 += __x2; \
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if (__x1 < __x2) \
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__x3 += __ll_B; \
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\
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(w1) = __x3 + __ll_highpart(__x1); \
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(w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0); \
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} while (0)
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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do { \
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UWtype __x; \
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__x = (al) + (bl); \
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(sh) = (ah) + (bh) + (__x < (al)); \
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(sl) = __x; \
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} while (0)
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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UWtype __x; \
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__x = (al) - (bl); \
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(sh) = (ah) - (bh) - (__x > (al)); \
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(sl) = __x; \
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} while (0)
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { \
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UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
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__d1 = __ll_highpart(d); \
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__d0 = __ll_lowpart(d); \
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\
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__r1 = (n1) % __d1; \
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__q1 = (n1) / __d1; \
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__m = (UWtype) __q1 * __d0; \
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__r1 = __r1 * __ll_B | __ll_highpart(n0); \
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if (__r1 < __m) { \
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__q1--, __r1 += (d); \
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if (__r1 >= (d)) \
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if (__r1 < __m) \
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__q1--, __r1 += (d); \
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} \
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__r1 -= __m; \
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__r0 = __r1 % __d1; \
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__q0 = __r1 / __d1; \
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__m = (UWtype) __q0 * __d0; \
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__r0 = __r0 * __ll_B | __ll_lowpart(n0); \
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if (__r0 < __m) { \
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__q0--, __r0 += (d); \
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if (__r0 >= (d)) \
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if (__r0 < __m) \
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__q0--, __r0 += (d); \
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} \
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__r0 -= __m; \
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(q) = (UWtype) __q1 * __ll_B | __q0; \
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(r) = __r0; \
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} while (0)
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