510 lines
13 KiB
ArmAsm
510 lines
13 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* linux/arch/arm/mm/arm925.S: MMU functions for ARM925
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*
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* Copyright (C) 1999,2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* Copyright (C) 2002 RidgeRun, Inc.
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* Copyright (C) 2002-2003 MontaVista Software, Inc.
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*
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* Update for Linux-2.6 and cache flush improvements
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* Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
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*
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* hacked for non-paged-MM by Hyok S. Choi, 2004.
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the arm925.
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*
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* CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
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*
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* Some additional notes based on deciphering the TI TRM on OMAP-5910:
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*
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* NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
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* entry mode" must be 0 to flush the entries in both segments
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* at once. This is the default value. See TRM 2-20 and 2-24 for
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* more information.
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*
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* NOTE2: Default is the "D-cache clean and flush entry mode". It looks
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* like the "Transparent mode" must be on for partial cache flushes
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* to work in this mode. This mode only works with 16-bit external
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* memory. See TRM 2-24 for more information.
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*
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* NOTE3: Write-back cache flushing seems to be flakey with devices using
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* direct memory access, such as USB OHCI. The workaround is to use
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* write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
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* the default for OMAP-1510).
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 16
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/*
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* The number of data cache segments.
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*/
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#define CACHE_DSEGMENTS 2
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/*
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* The number of lines in a cache segment.
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*/
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#define CACHE_DENTRIES 256
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/*
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* This is the size at which it becomes more efficient to
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* clean the whole cache, rather than using the individual
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* cache line maintenance instructions.
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*/
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#define CACHE_DLIMIT 8192
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.text
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/*
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* cpu_arm925_proc_init()
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*/
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ENTRY(cpu_arm925_proc_init)
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ret lr
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/*
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* cpu_arm925_proc_fin()
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*/
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ENTRY(cpu_arm925_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ret lr
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/*
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* cpu_arm925_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm925_reset)
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/* Send software reset to MPU and DSP */
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mov ip, #0xff000000
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orr ip, ip, #0x00fe0000
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orr ip, ip, #0x0000ce00
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mov r4, #1
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strh r4, [ip, #0x10]
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ENDPROC(cpu_arm925_reset)
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.popsection
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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ret r0
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/*
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* cpu_arm925_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 10
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ENTRY(cpu_arm925_do_idle)
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mov r0, #0
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mrc p15, 0, r1, c1, c0, 0 @ Read control register
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bic r2, r1, #1 << 12
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mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
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ret lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(arm925_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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ret lr
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ENDPROC(arm925_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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ENTRY(arm925_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm925_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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/* Flush entries in both segments at once, see NOTE1 above */
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mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
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2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
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subs r3, r3, #1 << 4
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bcs 2b @ entries 255 to 0
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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ENTRY(arm925_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#else
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#endif
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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ret lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm925_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm925_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov r0, #0
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(arm925_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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arm925_dma_inv_range:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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#endif
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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arm925_dma_clean_range:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm925_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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#else
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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#endif
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm925_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq arm925_dma_clean_range
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bcs arm925_dma_inv_range
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b arm925_dma_flush_range
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ENDPROC(arm925_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
|
||
|
|
*/
|
||
|
|
ENTRY(arm925_dma_unmap_area)
|
||
|
|
ret lr
|
||
|
|
ENDPROC(arm925_dma_unmap_area)
|
||
|
|
|
||
|
|
.globl arm925_flush_kern_cache_louis
|
||
|
|
.equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all
|
||
|
|
|
||
|
|
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
|
||
|
|
define_cache_functions arm925
|
||
|
|
|
||
|
|
ENTRY(cpu_arm925_dcache_clean_area)
|
||
|
|
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||
|
|
add r0, r0, #CACHE_DLINESIZE
|
||
|
|
subs r1, r1, #CACHE_DLINESIZE
|
||
|
|
bhi 1b
|
||
|
|
#endif
|
||
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||
|
|
ret lr
|
||
|
|
|
||
|
|
/* =============================== PageTable ============================== */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* cpu_arm925_switch_mm(pgd)
|
||
|
|
*
|
||
|
|
* Set the translation base pointer to be as described by pgd.
|
||
|
|
*
|
||
|
|
* pgd: new page tables
|
||
|
|
*/
|
||
|
|
.align 5
|
||
|
|
ENTRY(cpu_arm925_switch_mm)
|
||
|
|
#ifdef CONFIG_MMU
|
||
|
|
mov ip, #0
|
||
|
|
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||
|
|
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
|
||
|
|
#else
|
||
|
|
/* Flush entries in bothe segments at once, see NOTE1 above */
|
||
|
|
mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
|
||
|
|
2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
|
||
|
|
subs r3, r3, #1 << 4
|
||
|
|
bcs 2b @ entries 255 to 0
|
||
|
|
#endif
|
||
|
|
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||
|
|
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||
|
|
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||
|
|
#endif
|
||
|
|
ret lr
|
||
|
|
|
||
|
|
/*
|
||
|
|
* cpu_arm925_set_pte_ext(ptep, pte, ext)
|
||
|
|
*
|
||
|
|
* Set a PTE and flush it out
|
||
|
|
*/
|
||
|
|
.align 5
|
||
|
|
ENTRY(cpu_arm925_set_pte_ext)
|
||
|
|
#ifdef CONFIG_MMU
|
||
|
|
armv3_set_pte_ext
|
||
|
|
mov r0, r0
|
||
|
|
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||
|
|
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||
|
|
#endif
|
||
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||
|
|
#endif /* CONFIG_MMU */
|
||
|
|
ret lr
|
||
|
|
|
||
|
|
.type __arm925_setup, #function
|
||
|
|
__arm925_setup:
|
||
|
|
mov r0, #0
|
||
|
|
|
||
|
|
/* Transparent on, D-cache clean & flush mode. See NOTE2 above */
|
||
|
|
orr r0,r0,#1 << 1 @ transparent mode on
|
||
|
|
mcr p15, 0, r0, c15, c1, 0 @ write TI config register
|
||
|
|
|
||
|
|
mov r0, #0
|
||
|
|
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||
|
|
#ifdef CONFIG_MMU
|
||
|
|
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||
|
|
mov r0, #4 @ disable write-back on caches explicitly
|
||
|
|
mcr p15, 7, r0, c15, c0, 0
|
||
|
|
#endif
|
||
|
|
|
||
|
|
adr r5, arm925_crval
|
||
|
|
ldmia r5, {r5, r6}
|
||
|
|
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||
|
|
bic r0, r0, r5
|
||
|
|
orr r0, r0, r6
|
||
|
|
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
||
|
|
orr r0, r0, #0x4000 @ .1.. .... .... ....
|
||
|
|
#endif
|
||
|
|
ret lr
|
||
|
|
.size __arm925_setup, . - __arm925_setup
|
||
|
|
|
||
|
|
/*
|
||
|
|
* R
|
||
|
|
* .RVI ZFRS BLDP WCAM
|
||
|
|
* .011 0001 ..11 1101
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
.type arm925_crval, #object
|
||
|
|
arm925_crval:
|
||
|
|
crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
|
||
|
|
|
||
|
|
__INITDATA
|
||
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
||
|
|
define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
|
||
|
|
|
||
|
|
.section ".rodata"
|
||
|
|
|
||
|
|
string cpu_arch_name, "armv4t"
|
||
|
|
string cpu_elf_name, "v4"
|
||
|
|
string cpu_arm925_name, "ARM925T"
|
||
|
|
|
||
|
|
.align
|
||
|
|
|
||
|
|
.section ".proc.info.init", #alloc
|
||
|
|
|
||
|
|
.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
|
||
|
|
.type __\name\()_proc_info,#object
|
||
|
|
__\name\()_proc_info:
|
||
|
|
.long \cpu_val
|
||
|
|
.long \cpu_mask
|
||
|
|
.long PMD_TYPE_SECT | \
|
||
|
|
PMD_SECT_CACHEABLE | \
|
||
|
|
PMD_BIT4 | \
|
||
|
|
PMD_SECT_AP_WRITE | \
|
||
|
|
PMD_SECT_AP_READ
|
||
|
|
.long PMD_TYPE_SECT | \
|
||
|
|
PMD_BIT4 | \
|
||
|
|
PMD_SECT_AP_WRITE | \
|
||
|
|
PMD_SECT_AP_READ
|
||
|
|
initfn __arm925_setup, __\name\()_proc_info
|
||
|
|
.long cpu_arch_name
|
||
|
|
.long cpu_elf_name
|
||
|
|
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
|
||
|
|
.long cpu_arm925_name
|
||
|
|
.long arm925_processor_functions
|
||
|
|
.long v4wbi_tlb_fns
|
||
|
|
.long v4wb_user_fns
|
||
|
|
.long arm925_cache_fns
|
||
|
|
.size __\name\()_proc_info, . - __\name\()_proc_info
|
||
|
|
.endm
|
||
|
|
|
||
|
|
arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
|
||
|
|
arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name
|