566 lines
13 KiB
C
566 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* L220/L310 cache controller support
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*
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* Copyright (C) 2016 ARM Limited
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*/
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#include <linux/errno.h>
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#include <linux/hrtimer.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/perf_event.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <asm/hardware/cache-l2x0.h>
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#define PMU_NR_COUNTERS 2
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static void __iomem *l2x0_base;
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static struct pmu *l2x0_pmu;
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static cpumask_t pmu_cpu;
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static const char *l2x0_name;
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static ktime_t l2x0_pmu_poll_period;
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static struct hrtimer l2x0_pmu_hrtimer;
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/*
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* The L220/PL310 PMU has two equivalent counters, Counter1 and Counter0.
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* Registers controlling these are laid out in pairs, in descending order, i.e.
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* the register for Counter1 comes first, followed by the register for
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* Counter0.
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* We ensure that idx 0 -> Counter0, and idx1 -> Counter1.
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*/
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static struct perf_event *events[PMU_NR_COUNTERS];
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/* Find an unused counter */
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static int l2x0_pmu_find_idx(void)
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{
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int i;
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for (i = 0; i < PMU_NR_COUNTERS; i++) {
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if (!events[i])
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return i;
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}
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return -1;
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}
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/* How many counters are allocated? */
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static int l2x0_pmu_num_active_counters(void)
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{
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int i, cnt = 0;
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for (i = 0; i < PMU_NR_COUNTERS; i++) {
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if (events[i])
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cnt++;
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}
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return cnt;
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}
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static void l2x0_pmu_counter_config_write(int idx, u32 val)
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{
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writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx);
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}
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static u32 l2x0_pmu_counter_read(int idx)
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{
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return readl_relaxed(l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
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}
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static void l2x0_pmu_counter_write(int idx, u32 val)
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{
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writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
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}
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static void __l2x0_pmu_enable(void)
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{
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u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL);
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val |= L2X0_EVENT_CNT_CTRL_ENABLE;
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writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
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}
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static void __l2x0_pmu_disable(void)
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{
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u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL);
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val &= ~L2X0_EVENT_CNT_CTRL_ENABLE;
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writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
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}
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static void l2x0_pmu_enable(struct pmu *pmu)
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{
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if (l2x0_pmu_num_active_counters() == 0)
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return;
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__l2x0_pmu_enable();
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}
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static void l2x0_pmu_disable(struct pmu *pmu)
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{
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if (l2x0_pmu_num_active_counters() == 0)
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return;
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__l2x0_pmu_disable();
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}
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static void warn_if_saturated(u32 count)
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{
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if (count != 0xffffffff)
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return;
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pr_warn_ratelimited("L2X0 counter saturated. Poll period too long\n");
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}
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static void l2x0_pmu_event_read(struct perf_event *event)
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{
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struct hw_perf_event *hw = &event->hw;
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u64 prev_count, new_count, mask;
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do {
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prev_count = local64_read(&hw->prev_count);
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new_count = l2x0_pmu_counter_read(hw->idx);
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} while (local64_xchg(&hw->prev_count, new_count) != prev_count);
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mask = GENMASK_ULL(31, 0);
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local64_add((new_count - prev_count) & mask, &event->count);
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warn_if_saturated(new_count);
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}
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static void l2x0_pmu_event_configure(struct perf_event *event)
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{
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struct hw_perf_event *hw = &event->hw;
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/*
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* The L2X0 counters saturate at 0xffffffff rather than wrapping, so we
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* will *always* lose some number of events when a counter saturates,
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* and have no way of detecting how many were lost.
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*
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* To minimize the impact of this, we try to maximize the period by
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* always starting counters at zero. To ensure that group ratios are
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* representative, we poll periodically to avoid counters saturating.
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* See l2x0_pmu_poll().
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*/
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local64_set(&hw->prev_count, 0);
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l2x0_pmu_counter_write(hw->idx, 0);
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}
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static enum hrtimer_restart l2x0_pmu_poll(struct hrtimer *hrtimer)
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{
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unsigned long flags;
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int i;
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local_irq_save(flags);
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__l2x0_pmu_disable();
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for (i = 0; i < PMU_NR_COUNTERS; i++) {
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struct perf_event *event = events[i];
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if (!event)
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continue;
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l2x0_pmu_event_read(event);
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l2x0_pmu_event_configure(event);
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}
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__l2x0_pmu_enable();
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local_irq_restore(flags);
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hrtimer_forward_now(hrtimer, l2x0_pmu_poll_period);
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return HRTIMER_RESTART;
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}
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static void __l2x0_pmu_event_enable(int idx, u32 event)
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{
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u32 val;
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val = event << L2X0_EVENT_CNT_CFG_SRC_SHIFT;
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val |= L2X0_EVENT_CNT_CFG_INT_DISABLED;
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l2x0_pmu_counter_config_write(idx, val);
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}
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static void l2x0_pmu_event_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hw = &event->hw;
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if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
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return;
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if (flags & PERF_EF_RELOAD) {
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WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
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l2x0_pmu_event_configure(event);
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}
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hw->state = 0;
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__l2x0_pmu_event_enable(hw->idx, hw->config_base);
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}
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static void __l2x0_pmu_event_disable(int idx)
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{
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u32 val;
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val = L2X0_EVENT_CNT_CFG_SRC_DISABLED << L2X0_EVENT_CNT_CFG_SRC_SHIFT;
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val |= L2X0_EVENT_CNT_CFG_INT_DISABLED;
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l2x0_pmu_counter_config_write(idx, val);
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}
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static void l2x0_pmu_event_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hw = &event->hw;
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if (WARN_ON_ONCE(event->hw.state & PERF_HES_STOPPED))
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return;
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__l2x0_pmu_event_disable(hw->idx);
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hw->state |= PERF_HES_STOPPED;
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if (flags & PERF_EF_UPDATE) {
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l2x0_pmu_event_read(event);
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hw->state |= PERF_HES_UPTODATE;
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}
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}
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static int l2x0_pmu_event_add(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hw = &event->hw;
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int idx = l2x0_pmu_find_idx();
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if (idx == -1)
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return -EAGAIN;
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/*
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* Pin the timer, so that the overflows are handled by the chosen
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* event->cpu (this is the same one as presented in "cpumask"
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* attribute).
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*/
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if (l2x0_pmu_num_active_counters() == 0)
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hrtimer_start(&l2x0_pmu_hrtimer, l2x0_pmu_poll_period,
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HRTIMER_MODE_REL_PINNED);
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events[idx] = event;
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hw->idx = idx;
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l2x0_pmu_event_configure(event);
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hw->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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l2x0_pmu_event_start(event, 0);
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return 0;
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}
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static void l2x0_pmu_event_del(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hw = &event->hw;
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l2x0_pmu_event_stop(event, PERF_EF_UPDATE);
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events[hw->idx] = NULL;
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hw->idx = -1;
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if (l2x0_pmu_num_active_counters() == 0)
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hrtimer_cancel(&l2x0_pmu_hrtimer);
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}
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static bool l2x0_pmu_group_is_valid(struct perf_event *event)
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{
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struct pmu *pmu = event->pmu;
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struct perf_event *leader = event->group_leader;
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struct perf_event *sibling;
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int num_hw = 0;
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if (leader->pmu == pmu)
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num_hw++;
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else if (!is_software_event(leader))
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return false;
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for_each_sibling_event(sibling, leader) {
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if (sibling->pmu == pmu)
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num_hw++;
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else if (!is_software_event(sibling))
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return false;
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}
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return num_hw <= PMU_NR_COUNTERS;
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}
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static int l2x0_pmu_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hw = &event->hw;
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if (event->attr.type != l2x0_pmu->type)
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return -ENOENT;
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if (is_sampling_event(event) ||
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event->attach_state & PERF_ATTACH_TASK)
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return -EINVAL;
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if (event->cpu < 0)
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return -EINVAL;
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if (event->attr.config & ~L2X0_EVENT_CNT_CFG_SRC_MASK)
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return -EINVAL;
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hw->config_base = event->attr.config;
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if (!l2x0_pmu_group_is_valid(event))
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return -EINVAL;
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event->cpu = cpumask_first(&pmu_cpu);
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return 0;
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}
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struct l2x0_event_attribute {
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struct device_attribute attr;
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unsigned int config;
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bool pl310_only;
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};
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#define L2X0_EVENT_ATTR(_name, _config, _pl310_only) \
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(&((struct l2x0_event_attribute[]) {{ \
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.attr = __ATTR(_name, S_IRUGO, l2x0_pmu_event_show, NULL), \
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.config = _config, \
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.pl310_only = _pl310_only, \
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}})[0].attr.attr)
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#define L220_PLUS_EVENT_ATTR(_name, _config) \
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L2X0_EVENT_ATTR(_name, _config, false)
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#define PL310_EVENT_ATTR(_name, _config) \
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L2X0_EVENT_ATTR(_name, _config, true)
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static ssize_t l2x0_pmu_event_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct l2x0_event_attribute *lattr;
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lattr = container_of(attr, typeof(*lattr), attr);
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return snprintf(buf, PAGE_SIZE, "config=0x%x\n", lattr->config);
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}
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static umode_t l2x0_pmu_event_attr_is_visible(struct kobject *kobj,
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struct attribute *attr,
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int unused)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct pmu *pmu = dev_get_drvdata(dev);
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struct l2x0_event_attribute *lattr;
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lattr = container_of(attr, typeof(*lattr), attr.attr);
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if (!lattr->pl310_only || strcmp("l2c_310", pmu->name) == 0)
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return attr->mode;
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return 0;
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}
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static struct attribute *l2x0_pmu_event_attrs[] = {
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L220_PLUS_EVENT_ATTR(co, 0x1),
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L220_PLUS_EVENT_ATTR(drhit, 0x2),
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L220_PLUS_EVENT_ATTR(drreq, 0x3),
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L220_PLUS_EVENT_ATTR(dwhit, 0x4),
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||
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L220_PLUS_EVENT_ATTR(dwreq, 0x5),
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||
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L220_PLUS_EVENT_ATTR(dwtreq, 0x6),
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|
|
L220_PLUS_EVENT_ATTR(irhit, 0x7),
|
||
|
|
L220_PLUS_EVENT_ATTR(irreq, 0x8),
|
||
|
|
L220_PLUS_EVENT_ATTR(wa, 0x9),
|
||
|
|
PL310_EVENT_ATTR(ipfalloc, 0xa),
|
||
|
|
PL310_EVENT_ATTR(epfhit, 0xb),
|
||
|
|
PL310_EVENT_ATTR(epfalloc, 0xc),
|
||
|
|
PL310_EVENT_ATTR(srrcvd, 0xd),
|
||
|
|
PL310_EVENT_ATTR(srconf, 0xe),
|
||
|
|
PL310_EVENT_ATTR(epfrcvd, 0xf),
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct attribute_group l2x0_pmu_event_attrs_group = {
|
||
|
|
.name = "events",
|
||
|
|
.attrs = l2x0_pmu_event_attrs,
|
||
|
|
.is_visible = l2x0_pmu_event_attr_is_visible,
|
||
|
|
};
|
||
|
|
|
||
|
|
static ssize_t l2x0_pmu_cpumask_show(struct device *dev,
|
||
|
|
struct device_attribute *attr, char *buf)
|
||
|
|
{
|
||
|
|
return cpumap_print_to_pagebuf(true, buf, &pmu_cpu);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct device_attribute l2x0_pmu_cpumask_attr =
|
||
|
|
__ATTR(cpumask, S_IRUGO, l2x0_pmu_cpumask_show, NULL);
|
||
|
|
|
||
|
|
static struct attribute *l2x0_pmu_cpumask_attrs[] = {
|
||
|
|
&l2x0_pmu_cpumask_attr.attr,
|
||
|
|
NULL,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct attribute_group l2x0_pmu_cpumask_attr_group = {
|
||
|
|
.attrs = l2x0_pmu_cpumask_attrs,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct attribute_group *l2x0_pmu_attr_groups[] = {
|
||
|
|
&l2x0_pmu_event_attrs_group,
|
||
|
|
&l2x0_pmu_cpumask_attr_group,
|
||
|
|
NULL,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void l2x0_pmu_reset(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
__l2x0_pmu_disable();
|
||
|
|
|
||
|
|
for (i = 0; i < PMU_NR_COUNTERS; i++)
|
||
|
|
__l2x0_pmu_event_disable(i);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int l2x0_pmu_offline_cpu(unsigned int cpu)
|
||
|
|
{
|
||
|
|
unsigned int target;
|
||
|
|
|
||
|
|
if (!cpumask_test_and_clear_cpu(cpu, &pmu_cpu))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
target = cpumask_any_but(cpu_online_mask, cpu);
|
||
|
|
if (target >= nr_cpu_ids)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
perf_pmu_migrate_context(l2x0_pmu, cpu, target);
|
||
|
|
cpumask_set_cpu(target, &pmu_cpu);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void l2x0_pmu_suspend(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (!l2x0_pmu)
|
||
|
|
return;
|
||
|
|
|
||
|
|
l2x0_pmu_disable(l2x0_pmu);
|
||
|
|
|
||
|
|
for (i = 0; i < PMU_NR_COUNTERS; i++) {
|
||
|
|
if (events[i])
|
||
|
|
l2x0_pmu_event_stop(events[i], PERF_EF_UPDATE);
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void l2x0_pmu_resume(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (!l2x0_pmu)
|
||
|
|
return;
|
||
|
|
|
||
|
|
l2x0_pmu_reset();
|
||
|
|
|
||
|
|
for (i = 0; i < PMU_NR_COUNTERS; i++) {
|
||
|
|
if (events[i])
|
||
|
|
l2x0_pmu_event_start(events[i], PERF_EF_RELOAD);
|
||
|
|
}
|
||
|
|
|
||
|
|
l2x0_pmu_enable(l2x0_pmu);
|
||
|
|
}
|
||
|
|
|
||
|
|
void __init l2x0_pmu_register(void __iomem *base, u32 part)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Determine whether we support the PMU, and choose the name for sysfs.
|
||
|
|
* This is also used by l2x0_pmu_event_attr_is_visible to determine
|
||
|
|
* which events to display, as the PL310 PMU supports a superset of
|
||
|
|
* L220 events.
|
||
|
|
*
|
||
|
|
* The L210 PMU has a different programmer's interface, and is not
|
||
|
|
* supported by this driver.
|
||
|
|
*
|
||
|
|
* We must defer registering the PMU until the perf subsystem is up and
|
||
|
|
* running, so just stash the name and base, and leave that to another
|
||
|
|
* initcall.
|
||
|
|
*/
|
||
|
|
switch (part & L2X0_CACHE_ID_PART_MASK) {
|
||
|
|
case L2X0_CACHE_ID_PART_L220:
|
||
|
|
l2x0_name = "l2c_220";
|
||
|
|
break;
|
||
|
|
case L2X0_CACHE_ID_PART_L310:
|
||
|
|
l2x0_name = "l2c_310";
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
l2x0_base = base;
|
||
|
|
}
|
||
|
|
|
||
|
|
static __init int l2x0_pmu_init(void)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!l2x0_base)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
l2x0_pmu = kzalloc(sizeof(*l2x0_pmu), GFP_KERNEL);
|
||
|
|
if (!l2x0_pmu) {
|
||
|
|
pr_warn("Unable to allocate L2x0 PMU\n");
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
*l2x0_pmu = (struct pmu) {
|
||
|
|
.task_ctx_nr = perf_invalid_context,
|
||
|
|
.pmu_enable = l2x0_pmu_enable,
|
||
|
|
.pmu_disable = l2x0_pmu_disable,
|
||
|
|
.read = l2x0_pmu_event_read,
|
||
|
|
.start = l2x0_pmu_event_start,
|
||
|
|
.stop = l2x0_pmu_event_stop,
|
||
|
|
.add = l2x0_pmu_event_add,
|
||
|
|
.del = l2x0_pmu_event_del,
|
||
|
|
.event_init = l2x0_pmu_event_init,
|
||
|
|
.attr_groups = l2x0_pmu_attr_groups,
|
||
|
|
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
|
||
|
|
};
|
||
|
|
|
||
|
|
l2x0_pmu_reset();
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We always use a hrtimer rather than an interrupt.
|
||
|
|
* See comments in l2x0_pmu_event_configure and l2x0_pmu_poll.
|
||
|
|
*
|
||
|
|
* Polling once a second allows the counters to fill up to 1/128th on a
|
||
|
|
* quad-core test chip with cores clocked at 400MHz. Hopefully this
|
||
|
|
* leaves sufficient headroom to avoid overflow on production silicon
|
||
|
|
* at higher frequencies.
|
||
|
|
*/
|
||
|
|
l2x0_pmu_poll_period = ms_to_ktime(1000);
|
||
|
|
hrtimer_init(&l2x0_pmu_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
||
|
|
l2x0_pmu_hrtimer.function = l2x0_pmu_poll;
|
||
|
|
|
||
|
|
cpumask_set_cpu(0, &pmu_cpu);
|
||
|
|
ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_L2X0_ONLINE,
|
||
|
|
"perf/arm/l2x0:online", NULL,
|
||
|
|
l2x0_pmu_offline_cpu);
|
||
|
|
if (ret)
|
||
|
|
goto out_pmu;
|
||
|
|
|
||
|
|
ret = perf_pmu_register(l2x0_pmu, l2x0_name, -1);
|
||
|
|
if (ret)
|
||
|
|
goto out_cpuhp;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
out_cpuhp:
|
||
|
|
cpuhp_remove_state_nocalls(CPUHP_AP_PERF_ARM_L2X0_ONLINE);
|
||
|
|
out_pmu:
|
||
|
|
kfree(l2x0_pmu);
|
||
|
|
l2x0_pmu = NULL;
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
device_initcall(l2x0_pmu_init);
|