42 lines
1011 B
C
42 lines
1011 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2012 Calxeda, Inc.
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*/
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#ifndef _ASM_ARM_PERCPU_H_
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#define _ASM_ARM_PERCPU_H_
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/*
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* Same as asm-generic/percpu.h, except that we store the per cpu offset
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* in the TPIDRPRW. TPIDRPRW only exists on V6K and V7
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*/
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#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6)
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static inline void set_my_cpu_offset(unsigned long off)
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{
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/* Set TPIDRPRW */
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asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory");
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}
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static inline unsigned long __my_cpu_offset(void)
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{
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unsigned long off;
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/*
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* Read TPIDRPRW.
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* We want to allow caching the value, so avoid using volatile and
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* instead use a fake stack read to hazard against barrier().
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*/
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asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off)
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: "Q" (*(const unsigned long *)current_stack_pointer));
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return off;
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}
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#define __my_cpu_offset __my_cpu_offset()
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#else
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#define set_my_cpu_offset(x) do {} while(0)
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#endif /* CONFIG_SMP */
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#include <asm-generic/percpu.h>
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#endif /* _ASM_ARM_PERCPU_H_ */
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