425 lines
12 KiB
C
425 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#ifndef __ARM_KVM_HOST_H__
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#define __ARM_KVM_HOST_H__
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/kvm_types.h>
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#include <asm/cputype.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/fpstate.h>
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#include <kvm/arm_arch_timer.h>
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED
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#define KVM_USER_MEM_SLOTS 32
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#define KVM_HAVE_ONE_REG
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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#define KVM_VCPU_MAX_FEATURES 2
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#include <kvm/arm_vgic.h>
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#ifdef CONFIG_ARM_GIC_V3
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#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
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#else
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#define KVM_MAX_VCPUS VGIC_V2_MAX_CPUS
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#endif
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#define KVM_REQ_SLEEP \
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KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
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#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
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#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
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DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
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static inline int kvm_arm_init_sve(void) { return 0; }
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u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
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int __attribute_const__ kvm_target_cpu(void);
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
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void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
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struct kvm_vmid {
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/* The VMID generation used for the virt. memory system */
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u64 vmid_gen;
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u32 vmid;
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};
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struct kvm_arch {
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/* The last vcpu id that ran on each physical CPU */
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int __percpu *last_vcpu_ran;
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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*/
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/* The VMID generation used for the virt. memory system */
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struct kvm_vmid vmid;
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/* Stage-2 page table */
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pgd_t *pgd;
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phys_addr_t pgd_phys;
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/* Interrupt controller */
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struct vgic_dist vgic;
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int max_vcpus;
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/* Mandated version of PSCI */
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u32 psci_version;
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};
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#define KVM_NR_MEM_OBJS 40
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/*
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* We don't want allocation failures within the mmu code, so we preallocate
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* enough memory for a single page fault in a cache.
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*/
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struct kvm_mmu_memory_cache {
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int nobjs;
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void *objects[KVM_NR_MEM_OBJS];
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};
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struct kvm_vcpu_fault_info {
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u32 hsr; /* Hyp Syndrome Register */
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u32 hxfar; /* Hyp Data/Inst. Fault Address Register */
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u32 hpfar; /* Hyp IPA Fault Address Register */
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};
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/*
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* 0 is reserved as an invalid value.
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* Order should be kept in sync with the save/restore code.
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*/
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enum vcpu_sysreg {
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__INVALID_SYSREG__,
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c0_MPIDR, /* MultiProcessor ID Register */
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c0_CSSELR, /* Cache Size Selection Register */
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c1_SCTLR, /* System Control Register */
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c1_ACTLR, /* Auxiliary Control Register */
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c1_CPACR, /* Coprocessor Access Control */
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c2_TTBR0, /* Translation Table Base Register 0 */
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c2_TTBR0_high, /* TTBR0 top 32 bits */
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c2_TTBR1, /* Translation Table Base Register 1 */
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c2_TTBR1_high, /* TTBR1 top 32 bits */
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c2_TTBCR, /* Translation Table Base Control R. */
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c3_DACR, /* Domain Access Control Register */
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c5_DFSR, /* Data Fault Status Register */
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c5_IFSR, /* Instruction Fault Status Register */
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c5_ADFSR, /* Auxilary Data Fault Status R */
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c5_AIFSR, /* Auxilary Instrunction Fault Status R */
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c6_DFAR, /* Data Fault Address Register */
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c6_IFAR, /* Instruction Fault Address Register */
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c7_PAR, /* Physical Address Register */
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c7_PAR_high, /* PAR top 32 bits */
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c9_L2CTLR, /* Cortex A15/A7 L2 Control Register */
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c10_PRRR, /* Primary Region Remap Register */
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c10_NMRR, /* Normal Memory Remap Register */
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c12_VBAR, /* Vector Base Address Register */
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c13_CID, /* Context ID Register */
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c13_TID_URW, /* Thread ID, User R/W */
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c13_TID_URO, /* Thread ID, User R/O */
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c13_TID_PRIV, /* Thread ID, Privileged */
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c14_CNTKCTL, /* Timer Control Register (PL1) */
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c10_AMAIR0, /* Auxilary Memory Attribute Indirection Reg0 */
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c10_AMAIR1, /* Auxilary Memory Attribute Indirection Reg1 */
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NR_CP15_REGS /* Number of regs (incl. invalid) */
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};
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struct kvm_cpu_context {
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struct kvm_regs gp_regs;
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struct vfp_hard_struct vfp;
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u32 cp15[NR_CP15_REGS];
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};
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struct kvm_host_data {
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struct kvm_cpu_context host_ctxt;
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};
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typedef struct kvm_host_data kvm_host_data_t;
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static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
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{
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/* The host's MPIDR is immutable, so let's set it up at boot time */
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cpu_ctxt->cp15[c0_MPIDR] = read_cpuid_mpidr();
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}
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struct vcpu_reset_state {
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unsigned long pc;
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unsigned long r0;
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bool be;
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bool reset;
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};
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struct kvm_vcpu_arch {
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struct kvm_cpu_context ctxt;
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int target; /* Processor target */
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DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
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/* The CPU type we expose to the VM */
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u32 midr;
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/* HYP trapping configuration */
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u32 hcr;
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/* Exception Information */
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struct kvm_vcpu_fault_info fault;
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/* Host FP context */
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struct kvm_cpu_context *host_cpu_context;
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/* VGIC state */
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struct vgic_cpu vgic_cpu;
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struct arch_timer_cpu timer_cpu;
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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*/
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/* vcpu power-off state */
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bool power_off;
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/* Don't run the guest (internal implementation need) */
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bool pause;
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/* IO related fields */
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struct kvm_decode mmio_decode;
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/* Cache some mmu pages needed inside spinlock regions */
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struct kvm_mmu_memory_cache mmu_page_cache;
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struct vcpu_reset_state reset_state;
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/* Detect first run of a vcpu */
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bool has_run_once;
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};
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struct kvm_vm_stat {
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ulong remote_tlb_flush;
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};
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struct kvm_vcpu_stat {
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u64 halt_successful_poll;
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u64 halt_attempted_poll;
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u64 halt_poll_invalid;
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u64 halt_wakeup;
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u64 hvc_exit_stat;
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u64 wfe_exit_stat;
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u64 wfi_exit_stat;
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u64 mmio_exit_user;
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u64 mmio_exit_kernel;
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u64 exits;
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};
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#define vcpu_cp15(v,r) (v)->arch.ctxt.cp15[r]
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int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
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unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
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int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
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int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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unsigned long __kvm_call_hyp(void *hypfn, ...);
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/*
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* The has_vhe() part doesn't get emitted, but is used for type-checking.
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*/
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#define kvm_call_hyp(f, ...) \
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do { \
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if (has_vhe()) { \
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f(__VA_ARGS__); \
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} else { \
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__kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \
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} \
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} while(0)
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#define kvm_call_hyp_ret(f, ...) \
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({ \
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typeof(f(__VA_ARGS__)) ret; \
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\
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if (has_vhe()) { \
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ret = f(__VA_ARGS__); \
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} else { \
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ret = __kvm_call_hyp(kvm_ksym_ref(f), \
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##__VA_ARGS__); \
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} \
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\
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ret; \
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})
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void force_vm_exit(const cpumask_t *mask);
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int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
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struct kvm_vcpu_events *events);
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int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
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struct kvm_vcpu_events *events);
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#define KVM_ARCH_WANT_MMU_NOTIFIER
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int kvm_unmap_hva_range(struct kvm *kvm,
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unsigned long start, unsigned long end);
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int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
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unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
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int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
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int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
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int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
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struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
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struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
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void kvm_arm_halt_guest(struct kvm *kvm);
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void kvm_arm_resume_guest(struct kvm *kvm);
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int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
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unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
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int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
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int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
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int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
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int exception_index);
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static inline void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
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int exception_index) {}
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static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
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unsigned long hyp_stack_ptr,
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unsigned long vector_ptr)
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{
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/*
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* Call initialization code, and switch to the full blown HYP
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* code. The init code doesn't need to preserve these
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* registers as r0-r3 are already callee saved according to
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* the AAPCS.
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* Note that we slightly misuse the prototype by casting the
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* stack pointer to a void *.
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* The PGDs are always passed as the third argument, in order
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* to be passed into r2-r3 to the init code (yes, this is
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* compliant with the PCS!).
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*/
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__kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr);
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}
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static inline void __cpu_init_stage2(void)
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{
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kvm_call_hyp(__init_stage2_translation);
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}
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static inline int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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{
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return 0;
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}
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int kvm_perf_init(void);
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int kvm_perf_teardown(void);
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void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
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struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
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static inline bool kvm_arch_requires_vhe(void) { return false; }
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static inline void kvm_arch_hardware_unsetup(void) {}
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static inline void kvm_arch_sync_events(struct kvm *kvm) {}
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static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
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static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arm_init_debug(void) {}
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static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {}
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int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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/*
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* VFP/NEON switching is all done by the hyp switch code, so no need to
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* coordinate with host context handling for this state:
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|
|
*/
|
||
|
|
static inline void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) {}
|
||
|
|
static inline void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) {}
|
||
|
|
static inline void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) {}
|
||
|
|
|
||
|
|
static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
|
||
|
|
static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
|
||
|
|
|
||
|
|
static inline void kvm_arm_vhe_guest_enter(void) {}
|
||
|
|
static inline void kvm_arm_vhe_guest_exit(void) {}
|
||
|
|
|
||
|
|
#define KVM_BP_HARDEN_UNKNOWN -1
|
||
|
|
#define KVM_BP_HARDEN_WA_NEEDED 0
|
||
|
|
#define KVM_BP_HARDEN_NOT_REQUIRED 1
|
||
|
|
|
||
|
|
static inline int kvm_arm_harden_branch_predictor(void)
|
||
|
|
{
|
||
|
|
switch(read_cpuid_part()) {
|
||
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
||
|
|
case ARM_CPU_PART_BRAHMA_B15:
|
||
|
|
case ARM_CPU_PART_CORTEX_A12:
|
||
|
|
case ARM_CPU_PART_CORTEX_A15:
|
||
|
|
case ARM_CPU_PART_CORTEX_A17:
|
||
|
|
return KVM_BP_HARDEN_WA_NEEDED;
|
||
|
|
#endif
|
||
|
|
case ARM_CPU_PART_CORTEX_A7:
|
||
|
|
return KVM_BP_HARDEN_NOT_REQUIRED;
|
||
|
|
default:
|
||
|
|
return KVM_BP_HARDEN_UNKNOWN;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#define KVM_SSBD_UNKNOWN -1
|
||
|
|
#define KVM_SSBD_FORCE_DISABLE 0
|
||
|
|
#define KVM_SSBD_KERNEL 1
|
||
|
|
#define KVM_SSBD_FORCE_ENABLE 2
|
||
|
|
#define KVM_SSBD_MITIGATED 3
|
||
|
|
|
||
|
|
static inline int kvm_arm_have_ssbd(void)
|
||
|
|
{
|
||
|
|
/* No way to detect it yet, pretend it is not there. */
|
||
|
|
return KVM_SSBD_UNKNOWN;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu) {}
|
||
|
|
static inline void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu) {}
|
||
|
|
|
||
|
|
#define __KVM_HAVE_ARCH_VM_ALLOC
|
||
|
|
struct kvm *kvm_arch_alloc_vm(void);
|
||
|
|
void kvm_arch_free_vm(struct kvm *kvm);
|
||
|
|
|
||
|
|
static inline int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* On 32bit ARM, VMs get a static 40bit IPA stage2 setup,
|
||
|
|
* so any non-zero value used as type is illegal.
|
||
|
|
*/
|
||
|
|
if (type)
|
||
|
|
return -EINVAL;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
|
||
|
|
{
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
|
||
|
|
{
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __ARM_KVM_HOST_H__ */
|