62 lines
4.3 KiB
JSON
62 lines
4.3 KiB
JSON
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[
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"PEBScounters": "0,1,2,3",
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"EventName": "ICACHE.HIT",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"PEBScounters": "0,1,2,3",
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"EventName": "ICACHE.MISSES",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x3",
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"PEBScounters": "0,1,2,3",
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"EventName": "ICACHE.ACCESSES",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
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"EventCode": "0xE7",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"PEBScounters": "0,1,2,3",
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"EventName": "MS_DECODED.MS_ENTRY",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "MS decode starts"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
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"EventCode": "0xE9",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"PEBScounters": "0,1,2,3",
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"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "Decode restrictions due to predicting wrong instruction length"
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}
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]
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