60 lines
1.5 KiB
ArmAsm
60 lines
1.5 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#define R0 0x00
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#define R1 0x08
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#define R2 0x10
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#define R3 0x18
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#define R4 0x20
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#define R5 0x28
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#define R6 0x30
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#define R7 0x38
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#define R8 0x40
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#define R9 0x48
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#define SL 0x50
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#define FP 0x58
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#define IP 0x60
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#define SP 0x68
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#define LR 0x70
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#define PC 0x78
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/*
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* Implementation of void perf_regs_load(u64 *regs);
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*
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* This functions fills in the 'regs' buffer from the actual registers values,
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* in the way the perf built-in unwinding test expects them:
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* - the PC at the time at the call to this function. Since this function
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* is called using a bl instruction, the PC value is taken from LR.
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* The built-in unwinding test then unwinds the call stack from the dwarf
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* information in unwind__get_entries.
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*
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* Notes:
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* - the 8 bytes stride in the registers offsets comes from the fact
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* that the registers are stored in an u64 array (u64 *regs),
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* - the regs buffer needs to be zeroed before the call to this function,
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* in this case using a calloc in dwarf-unwind.c.
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*/
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.text
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.type perf_regs_load,%function
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ENTRY(perf_regs_load)
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str r0, [r0, #R0]
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str r1, [r0, #R1]
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str r2, [r0, #R2]
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str r3, [r0, #R3]
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str r4, [r0, #R4]
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str r5, [r0, #R5]
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str r6, [r0, #R6]
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str r7, [r0, #R7]
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str r8, [r0, #R8]
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str r9, [r0, #R9]
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str sl, [r0, #SL]
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str fp, [r0, #FP]
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str ip, [r0, #IP]
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str sp, [r0, #SP]
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str lr, [r0, #LR]
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str lr, [r0, #PC] // store pc as lr in order to skip the call
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// to this function
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mov pc, lr
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ENDPROC(perf_regs_load)
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