615 lines
16 KiB
C
615 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Socionext Inc.
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*/
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#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#define USIO_NAME "mlb-usio-uart"
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#define USIO_UART_DEV_NAME "ttyUSI"
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static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
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#define RX 0
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#define TX 1
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static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
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#define MLB_USIO_REG_SMR 0
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#define MLB_USIO_REG_SCR 1
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#define MLB_USIO_REG_ESCR 2
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#define MLB_USIO_REG_SSR 3
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#define MLB_USIO_REG_DR 4
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#define MLB_USIO_REG_BGR 6
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#define MLB_USIO_REG_FCR 12
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#define MLB_USIO_REG_FBYTE 14
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#define MLB_USIO_SMR_SOE BIT(0)
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#define MLB_USIO_SMR_SBL BIT(3)
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#define MLB_USIO_SCR_TXE BIT(0)
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#define MLB_USIO_SCR_RXE BIT(1)
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#define MLB_USIO_SCR_TBIE BIT(2)
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#define MLB_USIO_SCR_TIE BIT(3)
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#define MLB_USIO_SCR_RIE BIT(4)
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#define MLB_USIO_SCR_UPCL BIT(7)
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#define MLB_USIO_ESCR_L_8BIT 0
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#define MLB_USIO_ESCR_L_5BIT 1
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#define MLB_USIO_ESCR_L_6BIT 2
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#define MLB_USIO_ESCR_L_7BIT 3
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#define MLB_USIO_ESCR_P BIT(3)
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#define MLB_USIO_ESCR_PEN BIT(4)
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#define MLB_USIO_ESCR_FLWEN BIT(7)
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#define MLB_USIO_SSR_TBI BIT(0)
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#define MLB_USIO_SSR_TDRE BIT(1)
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#define MLB_USIO_SSR_RDRF BIT(2)
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#define MLB_USIO_SSR_ORE BIT(3)
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#define MLB_USIO_SSR_FRE BIT(4)
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#define MLB_USIO_SSR_PE BIT(5)
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#define MLB_USIO_SSR_REC BIT(7)
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#define MLB_USIO_SSR_BRK BIT(8)
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#define MLB_USIO_FCR_FE1 BIT(0)
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#define MLB_USIO_FCR_FE2 BIT(1)
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#define MLB_USIO_FCR_FCL1 BIT(2)
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#define MLB_USIO_FCR_FCL2 BIT(3)
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#define MLB_USIO_FCR_FSET BIT(4)
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#define MLB_USIO_FCR_FTIE BIT(9)
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#define MLB_USIO_FCR_FDRQ BIT(10)
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#define MLB_USIO_FCR_FRIIE BIT(11)
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static void mlb_usio_stop_tx(struct uart_port *port)
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{
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writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
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port->membase + MLB_USIO_REG_FCR);
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writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
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port->membase + MLB_USIO_REG_SCR);
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}
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static void mlb_usio_tx_chars(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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int count;
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writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
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port->membase + MLB_USIO_REG_FCR);
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writeb(readb(port->membase + MLB_USIO_REG_SCR) &
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~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE),
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port->membase + MLB_USIO_REG_SCR);
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if (port->x_char) {
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writew(port->x_char, port->membase + MLB_USIO_REG_DR);
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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mlb_usio_stop_tx(port);
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return;
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}
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count = port->fifosize -
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(readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
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do {
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writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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} while (--count > 0);
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writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
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port->membase + MLB_USIO_REG_FCR);
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writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
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port->membase + MLB_USIO_REG_SCR);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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mlb_usio_stop_tx(port);
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}
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static void mlb_usio_start_tx(struct uart_port *port)
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{
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u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
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writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
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if (!(fcr & MLB_USIO_FCR_FDRQ))
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return;
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writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
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port->membase + MLB_USIO_REG_SCR);
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if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
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mlb_usio_tx_chars(port);
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}
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static void mlb_usio_stop_rx(struct uart_port *port)
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{
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writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
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port->membase + MLB_USIO_REG_SCR);
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}
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static void mlb_usio_enable_ms(struct uart_port *port)
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{
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writeb(readb(port->membase + MLB_USIO_REG_SCR) |
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MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE,
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port->membase + MLB_USIO_REG_SCR);
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}
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static void mlb_usio_rx_chars(struct uart_port *port)
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{
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struct tty_port *ttyport = &port->state->port;
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unsigned long flag = 0;
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char ch = 0;
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u8 status;
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int max_count = 2;
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while (max_count--) {
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status = readb(port->membase + MLB_USIO_REG_SSR);
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if (!(status & MLB_USIO_SSR_RDRF))
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break;
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if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE |
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MLB_USIO_SSR_PE))) {
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ch = readw(port->membase + MLB_USIO_REG_DR);
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flag = TTY_NORMAL;
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port->icount.rx++;
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if (uart_handle_sysrq_char(port, ch))
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continue;
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uart_insert_char(port, status, MLB_USIO_SSR_ORE,
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ch, flag);
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continue;
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}
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if (status & MLB_USIO_SSR_PE)
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port->icount.parity++;
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if (status & MLB_USIO_SSR_ORE)
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port->icount.overrun++;
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status &= port->read_status_mask;
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if (status & MLB_USIO_SSR_BRK) {
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flag = TTY_BREAK;
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ch = 0;
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} else
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if (status & MLB_USIO_SSR_PE) {
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flag = TTY_PARITY;
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ch = 0;
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} else
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if (status & MLB_USIO_SSR_FRE) {
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flag = TTY_FRAME;
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ch = 0;
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}
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if (flag)
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uart_insert_char(port, status, MLB_USIO_SSR_ORE,
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ch, flag);
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writeb(readb(port->membase + MLB_USIO_REG_SSR) |
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MLB_USIO_SSR_REC,
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port->membase + MLB_USIO_REG_SSR);
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max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
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writew(readw(port->membase + MLB_USIO_REG_FCR) |
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MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
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port->membase + MLB_USIO_REG_FCR);
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}
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tty_flip_buffer_push(ttyport);
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}
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static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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spin_lock(&port->lock);
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mlb_usio_rx_chars(port);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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spin_lock(&port->lock);
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if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
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mlb_usio_tx_chars(port);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static unsigned int mlb_usio_tx_empty(struct uart_port *port)
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{
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return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
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TIOCSER_TEMT : 0;
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}
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static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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}
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static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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}
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static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int mlb_usio_startup(struct uart_port *port)
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{
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const char *portname = to_platform_device(port->dev)->name;
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unsigned long flags;
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int ret, index = port->line;
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unsigned char escr;
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ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq,
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0, portname, port);
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if (ret)
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return ret;
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ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq,
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0, portname, port);
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if (ret) {
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free_irq(mlb_usio_irq[index][RX], port);
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return ret;
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}
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escr = readb(port->membase + MLB_USIO_REG_ESCR);
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if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
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escr |= MLB_USIO_ESCR_FLWEN;
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spin_lock_irqsave(&port->lock, flags);
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writeb(0, port->membase + MLB_USIO_REG_SCR);
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writeb(escr, port->membase + MLB_USIO_REG_ESCR);
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writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
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writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
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writew(0, port->membase + MLB_USIO_REG_FCR);
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writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
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port->membase + MLB_USIO_REG_FCR);
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writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
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port->membase + MLB_USIO_REG_FCR);
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writew(0, port->membase + MLB_USIO_REG_FBYTE);
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writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
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writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE |
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MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
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spin_unlock_irqrestore(&port->lock, flags);
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return 0;
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}
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static void mlb_usio_shutdown(struct uart_port *port)
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{
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int index = port->line;
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free_irq(mlb_usio_irq[index][RX], port);
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free_irq(mlb_usio_irq[index][TX], port);
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}
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static void mlb_usio_set_termios(struct uart_port *port,
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struct ktermios *termios, struct ktermios *old)
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{
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unsigned int escr, smr = MLB_USIO_SMR_SOE;
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unsigned long flags, baud, quot;
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switch (termios->c_cflag & CSIZE) {
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case CS5:
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escr = MLB_USIO_ESCR_L_5BIT;
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break;
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case CS6:
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escr = MLB_USIO_ESCR_L_6BIT;
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break;
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case CS7:
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escr = MLB_USIO_ESCR_L_7BIT;
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break;
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case CS8:
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default:
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escr = MLB_USIO_ESCR_L_8BIT;
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break;
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}
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if (termios->c_cflag & CSTOPB)
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smr |= MLB_USIO_SMR_SBL;
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if (termios->c_cflag & PARENB) {
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escr |= MLB_USIO_ESCR_PEN;
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if (termios->c_cflag & PARODD)
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escr |= MLB_USIO_ESCR_P;
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}
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/* Set hard flow control */
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if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
|
||
|
|
(termios->c_cflag & CRTSCTS))
|
||
|
|
escr |= MLB_USIO_ESCR_FLWEN;
|
||
|
|
|
||
|
|
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
|
||
|
|
if (baud > 1)
|
||
|
|
quot = port->uartclk / baud - 1;
|
||
|
|
else
|
||
|
|
quot = 0;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&port->lock, flags);
|
||
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
||
|
|
port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
|
||
|
|
MLB_USIO_SSR_TDRE;
|
||
|
|
if (termios->c_iflag & INPCK)
|
||
|
|
port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
|
||
|
|
|
||
|
|
port->ignore_status_mask = 0;
|
||
|
|
if (termios->c_iflag & IGNPAR)
|
||
|
|
port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
|
||
|
|
if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR))
|
||
|
|
port->ignore_status_mask |= MLB_USIO_SSR_ORE;
|
||
|
|
if ((termios->c_cflag & CREAD) == 0)
|
||
|
|
port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
|
||
|
|
|
||
|
|
writeb(0, port->membase + MLB_USIO_REG_SCR);
|
||
|
|
writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
|
||
|
|
writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
|
||
|
|
writew(0, port->membase + MLB_USIO_REG_FCR);
|
||
|
|
writeb(smr, port->membase + MLB_USIO_REG_SMR);
|
||
|
|
writeb(escr, port->membase + MLB_USIO_REG_ESCR);
|
||
|
|
writew(quot, port->membase + MLB_USIO_REG_BGR);
|
||
|
|
writew(0, port->membase + MLB_USIO_REG_FCR);
|
||
|
|
writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 |
|
||
|
|
MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
|
||
|
|
port->membase + MLB_USIO_REG_FCR);
|
||
|
|
writew(0, port->membase + MLB_USIO_REG_FBYTE);
|
||
|
|
writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
|
||
|
|
writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE |
|
||
|
|
MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
|
||
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const char *mlb_usio_type(struct uart_port *port)
|
||
|
|
{
|
||
|
|
return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mlb_usio_config_port(struct uart_port *port, int flags)
|
||
|
|
{
|
||
|
|
if (flags & UART_CONFIG_TYPE)
|
||
|
|
port->type = PORT_MLB_USIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct uart_ops mlb_usio_ops = {
|
||
|
|
.tx_empty = mlb_usio_tx_empty,
|
||
|
|
.set_mctrl = mlb_usio_set_mctrl,
|
||
|
|
.get_mctrl = mlb_usio_get_mctrl,
|
||
|
|
.stop_tx = mlb_usio_stop_tx,
|
||
|
|
.start_tx = mlb_usio_start_tx,
|
||
|
|
.stop_rx = mlb_usio_stop_rx,
|
||
|
|
.enable_ms = mlb_usio_enable_ms,
|
||
|
|
.break_ctl = mlb_usio_break_ctl,
|
||
|
|
.startup = mlb_usio_startup,
|
||
|
|
.shutdown = mlb_usio_shutdown,
|
||
|
|
.set_termios = mlb_usio_set_termios,
|
||
|
|
.type = mlb_usio_type,
|
||
|
|
.config_port = mlb_usio_config_port,
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE
|
||
|
|
|
||
|
|
static void mlb_usio_console_putchar(struct uart_port *port, int c)
|
||
|
|
{
|
||
|
|
while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
|
||
|
|
cpu_relax();
|
||
|
|
|
||
|
|
writew(c, port->membase + MLB_USIO_REG_DR);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mlb_usio_console_write(struct console *co, const char *s,
|
||
|
|
unsigned int count)
|
||
|
|
{
|
||
|
|
struct uart_port *port = &mlb_usio_ports[co->index];
|
||
|
|
|
||
|
|
uart_console_write(port, s, count, mlb_usio_console_putchar);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init mlb_usio_console_setup(struct console *co, char *options)
|
||
|
|
{
|
||
|
|
struct uart_port *port;
|
||
|
|
int baud = 115200;
|
||
|
|
int parity = 'n';
|
||
|
|
int flow = 'n';
|
||
|
|
int bits = 8;
|
||
|
|
|
||
|
|
if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
port = &mlb_usio_ports[co->index];
|
||
|
|
if (!port->membase)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
|
||
|
|
if (options)
|
||
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||
|
|
|
||
|
|
if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
|
||
|
|
flow = 'r';
|
||
|
|
|
||
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static struct uart_driver mlb_usio_uart_driver;
|
||
|
|
static struct console mlb_usio_console = {
|
||
|
|
.name = USIO_UART_DEV_NAME,
|
||
|
|
.write = mlb_usio_console_write,
|
||
|
|
.device = uart_console_device,
|
||
|
|
.setup = mlb_usio_console_setup,
|
||
|
|
.flags = CON_PRINTBUFFER,
|
||
|
|
.index = -1,
|
||
|
|
.data = &mlb_usio_uart_driver,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init mlb_usio_console_init(void)
|
||
|
|
{
|
||
|
|
register_console(&mlb_usio_console);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
console_initcall(mlb_usio_console_init);
|
||
|
|
|
||
|
|
|
||
|
|
static void mlb_usio_early_console_write(struct console *co, const char *s,
|
||
|
|
u_int count)
|
||
|
|
{
|
||
|
|
struct earlycon_device *dev = co->data;
|
||
|
|
|
||
|
|
uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init mlb_usio_early_console_setup(struct earlycon_device *device,
|
||
|
|
const char *opt)
|
||
|
|
{
|
||
|
|
if (!device->port.membase)
|
||
|
|
return -ENODEV;
|
||
|
|
device->con->write = mlb_usio_early_console_write;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart",
|
||
|
|
mlb_usio_early_console_setup);
|
||
|
|
|
||
|
|
#define USIO_CONSOLE (&mlb_usio_console)
|
||
|
|
#else
|
||
|
|
#define USIO_CONSOLE NULL
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static struct uart_driver mlb_usio_uart_driver = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.driver_name = USIO_NAME,
|
||
|
|
.dev_name = USIO_UART_DEV_NAME,
|
||
|
|
.cons = USIO_CONSOLE,
|
||
|
|
.nr = CONFIG_SERIAL_MILBEAUT_USIO_PORTS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int mlb_usio_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct clk *clk = devm_clk_get(&pdev->dev, NULL);
|
||
|
|
struct uart_port *port;
|
||
|
|
struct resource *res;
|
||
|
|
int index = 0;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (IS_ERR(clk)) {
|
||
|
|
dev_err(&pdev->dev, "Missing clock\n");
|
||
|
|
return PTR_ERR(clk);
|
||
|
|
}
|
||
|
|
ret = clk_prepare_enable(clk);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "Clock enable failed: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
of_property_read_u32(pdev->dev.of_node, "index", &index);
|
||
|
|
port = &mlb_usio_ports[index];
|
||
|
|
|
||
|
|
port->private_data = (void *)clk;
|
||
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
|
if (res == NULL) {
|
||
|
|
dev_err(&pdev->dev, "Missing regs\n");
|
||
|
|
ret = -ENODEV;
|
||
|
|
goto failed;
|
||
|
|
}
|
||
|
|
port->membase = devm_ioremap(&pdev->dev, res->start,
|
||
|
|
resource_size(res));
|
||
|
|
|
||
|
|
ret = platform_get_irq_byname(pdev, "rx");
|
||
|
|
mlb_usio_irq[index][RX] = ret;
|
||
|
|
|
||
|
|
ret = platform_get_irq_byname(pdev, "tx");
|
||
|
|
mlb_usio_irq[index][TX] = ret;
|
||
|
|
|
||
|
|
port->irq = mlb_usio_irq[index][RX];
|
||
|
|
port->uartclk = clk_get_rate(clk);
|
||
|
|
port->fifosize = 128;
|
||
|
|
port->iotype = UPIO_MEM32;
|
||
|
|
port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
|
||
|
|
port->line = index;
|
||
|
|
port->ops = &mlb_usio_ops;
|
||
|
|
port->dev = &pdev->dev;
|
||
|
|
|
||
|
|
ret = uart_add_one_port(&mlb_usio_uart_driver, port);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
|
||
|
|
goto failed;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
failed:
|
||
|
|
clk_disable_unprepare(clk);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mlb_usio_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct uart_port *port = &mlb_usio_ports[pdev->id];
|
||
|
|
struct clk *clk = port->private_data;
|
||
|
|
|
||
|
|
uart_remove_one_port(&mlb_usio_uart_driver, port);
|
||
|
|
clk_disable_unprepare(clk);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id mlb_usio_dt_ids[] = {
|
||
|
|
{ .compatible = "socionext,milbeaut-usio-uart" },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids);
|
||
|
|
|
||
|
|
static struct platform_driver mlb_usio_driver = {
|
||
|
|
.probe = mlb_usio_probe,
|
||
|
|
.remove = mlb_usio_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = USIO_NAME,
|
||
|
|
.of_match_table = mlb_usio_dt_ids,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init mlb_usio_init(void)
|
||
|
|
{
|
||
|
|
int ret = uart_register_driver(&mlb_usio_uart_driver);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
pr_err("%s: uart registration failed: %d\n", __func__, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
ret = platform_driver_register(&mlb_usio_driver);
|
||
|
|
if (ret) {
|
||
|
|
uart_unregister_driver(&mlb_usio_uart_driver);
|
||
|
|
pr_err("%s: drv registration failed: %d\n", __func__, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit mlb_usio_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&mlb_usio_driver);
|
||
|
|
uart_unregister_driver(&mlb_usio_uart_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(mlb_usio_init);
|
||
|
|
module_exit(mlb_usio_exit);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("SOCIONEXT");
|
||
|
|
MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver");
|
||
|
|
MODULE_LICENSE("GPL");
|