258 lines
7.7 KiB
C
258 lines
7.7 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
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/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
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#ifndef _MLXSW_PCI_HW_H
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#define _MLXSW_PCI_HW_H
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#include <linux/bitops.h>
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#include "item.h"
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#define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
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#define MLXSW_PCI_PAGE_SIZE 4096
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#define MLXSW_PCI_CIR_BASE 0x71000
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#define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE
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#define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
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#define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
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#define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
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#define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
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#define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
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#define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
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#define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)
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#define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)
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#define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
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#define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24
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#define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000
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#define MLXSW_PCI_SW_RESET 0xF0010
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#define MLXSW_PCI_SW_RESET_RST_BIT BIT(0)
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#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 20000
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#define MLXSW_PCI_SW_RESET_WAIT_MSECS 100
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#define MLXSW_PCI_FW_READY 0xA1844
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#define MLXSW_PCI_FW_READY_MASK 0xFFFF
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#define MLXSW_PCI_FW_READY_MAGIC 0x5E
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#define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
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#define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
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#define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
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#define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
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#define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
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#define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
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#define MLXSW_PCI_DOORBELL(offset, type_offset, num) \
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((offset) + (type_offset) + (num) * 4)
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#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset) (offset)
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#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset) ((offset) + 4)
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#define MLXSW_PCI_CQS_MAX 96
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#define MLXSW_PCI_EQS_COUNT 2
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#define MLXSW_PCI_EQ_ASYNC_NUM 0
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#define MLXSW_PCI_EQ_COMP_NUM 1
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#define MLXSW_PCI_AQ_PAGES 8
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#define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
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#define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */
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#define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */
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#define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */
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#define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE
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#define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */
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#define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
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#define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
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#define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
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#define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
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#define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
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#define MLXSW_PCI_WQE_SG_ENTRIES 3
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#define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
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/* pci_wqe_c
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* If set it indicates that a completion should be reported upon
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* execution of this descriptor.
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*/
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MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
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/* pci_wqe_lp
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* Local Processing, set if packet should be processed by the local
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* switch hardware:
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* For Ethernet EMAD (Direct Route and non Direct Route) -
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* must be set if packet destination is local device
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* For InfiniBand CTL - must be set if packet destination is local device
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* Otherwise it must be clear
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* Local Process packets must not exceed the size of 2K (including payload
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* and headers).
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*/
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MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
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/* pci_wqe_type
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* Packet type.
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*/
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MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
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/* pci_wqe_byte_count
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* Size of i-th scatter/gather entry, 0 if entry is unused.
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*/
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MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
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/* pci_wqe_address
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* Physical address of i-th scatter/gather entry.
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* Gather Entries must be 2Byte aligned.
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*/
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MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
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enum mlxsw_pci_cqe_v {
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MLXSW_PCI_CQE_V0,
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MLXSW_PCI_CQE_V1,
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MLXSW_PCI_CQE_V2,
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};
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#define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \
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static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
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{ \
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switch (v) { \
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default: \
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case MLXSW_PCI_CQE_V0: \
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return mlxsw_pci_cqe##v0##_##name##_get(cqe); \
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case MLXSW_PCI_CQE_V1: \
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return mlxsw_pci_cqe##v1##_##name##_get(cqe); \
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case MLXSW_PCI_CQE_V2: \
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return mlxsw_pci_cqe##v2##_##name##_get(cqe); \
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} \
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} \
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static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \
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char *cqe, u32 val) \
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{ \
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switch (v) { \
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default: \
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case MLXSW_PCI_CQE_V0: \
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mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \
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break; \
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case MLXSW_PCI_CQE_V1: \
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mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \
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break; \
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case MLXSW_PCI_CQE_V2: \
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mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \
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break; \
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} \
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}
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/* pci_cqe_lag
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* Packet arrives from a port which is a LAG
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*/
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MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
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MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
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mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
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/* pci_cqe_system_port/lag_id
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* When lag=0: System port on which the packet was received
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* When lag=1:
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* bits [15:4] LAG ID on which the packet was received
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* bits [3:0] sub_port on which the packet was received
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*/
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MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
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MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
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MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
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mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
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MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
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MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
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mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
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/* pci_cqe_wqe_counter
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* WQE count of the WQEs completed on the associated dqn
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*/
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MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
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/* pci_cqe_byte_count
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* Byte count of received packets including additional two
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* Reserved Bytes that are append to the end of the frame.
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* Reserved for Send CQE.
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*/
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MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
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/* pci_cqe_trap_id
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* Trap ID that captured the packet.
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*/
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MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
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/* pci_cqe_crc
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* Length include CRC. Indicates the length field includes
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* the packet's CRC.
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*/
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MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
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MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
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mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
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/* pci_cqe_e
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* CQE with Error.
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*/
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MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
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MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
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mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
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/* pci_cqe_sr
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* 1 - Send Queue
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* 0 - Receive Queue
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*/
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MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
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MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
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mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
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/* pci_cqe_dqn
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* Descriptor Queue (DQ) Number.
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*/
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MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
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MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
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mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
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/* pci_cqe_owner
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* Ownership bit.
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*/
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MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
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MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
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mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
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/* pci_eqe_event_type
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* Event type.
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*/
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MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
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#define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
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#define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
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/* pci_eqe_event_sub_type
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* Event type.
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*/
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MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
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/* pci_eqe_cqn
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* Completion Queue that triggered this EQE.
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*/
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MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
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/* pci_eqe_owner
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* Ownership bit.
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*/
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MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
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/* pci_eqe_cmd_token
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* Command completion event - token
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*/
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MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
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/* pci_eqe_cmd_status
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* Command completion event - status
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*/
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MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
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/* pci_eqe_cmd_out_param_h
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* Command completion event - output parameter - higher part
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*/
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MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
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/* pci_eqe_cmd_out_param_l
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* Command completion event - output parameter - lower part
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*/
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MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
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#endif
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