141 lines
5.2 KiB
C
141 lines
5.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*/
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#ifndef HINIC_HW_CSR_H
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#define HINIC_HW_CSR_H
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/* HW interface registers */
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#define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
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#define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
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#define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
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#define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
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#define HINIC_DMA_ATTR_BASE 0xC80
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#define HINIC_ELECTION_BASE 0x4200
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#define HINIC_DMA_ATTR_STRIDE 0x4
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#define HINIC_CSR_DMA_ATTR_ADDR(idx) \
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(HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
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#define HINIC_PPF_ELECTION_STRIDE 0x4
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#define HINIC_CSR_MAX_PORTS 4
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#define HINIC_CSR_PPF_ELECTION_ADDR(idx) \
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(HINIC_ELECTION_BASE + (idx) * HINIC_PPF_ELECTION_STRIDE)
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/* API CMD registers */
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#define HINIC_CSR_API_CMD_BASE 0xF000
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#define HINIC_CSR_API_CMD_STRIDE 0x100
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#define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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#define HINIC_CSR_API_CMD_STATUS_ADDR(idx) \
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(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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/* MSI-X registers */
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#define HINIC_CSR_MSIX_CTRL_BASE 0x2000
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#define HINIC_CSR_MSIX_CNT_BASE 0x2004
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#define HINIC_CSR_MSIX_STRIDE 0x8
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#define HINIC_CSR_MSIX_CTRL_ADDR(idx) \
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(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
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#define HINIC_CSR_MSIX_CNT_ADDR(idx) \
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(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
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/* EQ registers */
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#define HINIC_AEQ_MTT_OFF_BASE_ADDR 0x200
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#define HINIC_CEQ_MTT_OFF_BASE_ADDR 0x400
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#define HINIC_EQ_MTT_OFF_STRIDE 0x40
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#define HINIC_CSR_AEQ_MTT_OFF(id) \
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(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
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#define HINIC_CSR_CEQ_MTT_OFF(id) \
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(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
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#define HINIC_CSR_EQ_PAGE_OFF_STRIDE 8
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#define HINIC_CSR_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) \
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(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
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(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
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#define HINIC_CSR_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num) \
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(HINIC_CSR_CEQ_MTT_OFF(q_id) + \
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(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
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#define HINIC_CSR_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) \
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(HINIC_CSR_AEQ_MTT_OFF(q_id) + \
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(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
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#define HINIC_CSR_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num) \
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(HINIC_CSR_CEQ_MTT_OFF(q_id) + \
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(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
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#define HINIC_AEQ_CTRL_0_ADDR_BASE 0xE00
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#define HINIC_AEQ_CTRL_1_ADDR_BASE 0xE04
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#define HINIC_AEQ_CONS_IDX_ADDR_BASE 0xE08
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#define HINIC_AEQ_PROD_IDX_ADDR_BASE 0xE0C
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#define HINIC_CEQ_CTRL_0_ADDR_BASE 0x1000
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#define HINIC_CEQ_CTRL_1_ADDR_BASE 0x1004
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#define HINIC_CEQ_CONS_IDX_ADDR_BASE 0x1008
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#define HINIC_CEQ_PROD_IDX_ADDR_BASE 0x100C
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#define HINIC_EQ_OFF_STRIDE 0x80
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#define HINIC_CSR_AEQ_CTRL_0_ADDR(idx) \
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(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_AEQ_CTRL_1_ADDR(idx) \
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(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx) \
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(HINIC_AEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx) \
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(HINIC_AEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_CEQ_CTRL_0_ADDR(idx) \
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(HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_CEQ_CTRL_1_ADDR(idx) \
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(HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx) \
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(HINIC_CEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx) \
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(HINIC_CEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
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#endif
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