396 lines
9.7 KiB
C
396 lines
9.7 KiB
C
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/*
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* Copyright 2015 Amazon.com, Inc. or its affiliates.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef ENA_H
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#define ENA_H
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#include <linux/bitops.h>
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#include <linux/dim.h>
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#include <linux/etherdevice.h>
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#include <linux/inetdevice.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/skbuff.h>
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#include "ena_com.h"
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#include "ena_eth_com.h"
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#define DRV_MODULE_VER_MAJOR 2
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#define DRV_MODULE_VER_MINOR 1
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#define DRV_MODULE_VER_SUBMINOR 0
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#define DRV_MODULE_NAME "ena"
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#ifndef DRV_MODULE_VERSION
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#define DRV_MODULE_VERSION \
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__stringify(DRV_MODULE_VER_MAJOR) "." \
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__stringify(DRV_MODULE_VER_MINOR) "." \
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__stringify(DRV_MODULE_VER_SUBMINOR) "K"
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#endif
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#define DEVICE_NAME "Elastic Network Adapter (ENA)"
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/* 1 for AENQ + ADMIN */
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#define ENA_ADMIN_MSIX_VEC 1
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#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
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/* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
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* driver passes 0.
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* Since the max packet size the ENA handles is ~9kB limit the buffer length to
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* 16kB.
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*/
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#if PAGE_SIZE > SZ_16K
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#define ENA_PAGE_SIZE SZ_16K
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#else
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#define ENA_PAGE_SIZE PAGE_SIZE
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#endif
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#define ENA_MIN_MSIX_VEC 2
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#define ENA_REG_BAR 0
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#define ENA_MEM_BAR 2
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#define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR))
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#define ENA_DEFAULT_RING_SIZE (1024)
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#define ENA_MIN_RING_SIZE (256)
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#define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2)
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#define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN)
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/* limit the buffer size to 600 bytes to handle MTU changes from very
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* small to very large, in which case the number of buffers per packet
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* could exceed ENA_PKT_MAX_BUFS
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*/
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#define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600
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#define ENA_MIN_MTU 128
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#define ENA_NAME_MAX_LEN 20
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#define ENA_IRQNAME_SIZE 40
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#define ENA_PKT_MAX_BUFS 19
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#define ENA_RX_RSS_TABLE_LOG_SIZE 7
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#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
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#define ENA_HASH_KEY_SIZE 40
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/* The number of tx packet completions that will be handled each NAPI poll
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* cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER.
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*/
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#define ENA_TX_POLL_BUDGET_DIVIDER 4
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/* Refill Rx queue when number of required descriptors is above
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* QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
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*/
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#define ENA_RX_REFILL_THRESH_DIVIDER 8
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#define ENA_RX_REFILL_THRESH_PACKET 256
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/* Number of queues to check for missing queues per timer service */
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#define ENA_MONITORED_TX_QUEUES 4
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/* Max timeout packets before device reset */
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#define MAX_NUM_OF_TIMEOUTED_PACKETS 128
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#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
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#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
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#define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \
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(((idx) + (n)) & ((ring_size) - 1))
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#define ENA_IO_TXQ_IDX(q) (2 * (q))
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#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
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#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
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#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
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#define ENA_MGMNT_IRQ_IDX 0
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#define ENA_IO_IRQ_FIRST_IDX 1
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#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
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/* ENA device should send keep alive msg every 1 sec.
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* We wait for 6 sec just to be on the safe side.
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*/
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#define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ)
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#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
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#define ENA_MMIO_DISABLE_REG_READ BIT(0)
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struct ena_irq {
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irq_handler_t handler;
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void *data;
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int cpu;
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u32 vector;
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cpumask_t affinity_hint_mask;
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char name[ENA_IRQNAME_SIZE];
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};
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struct ena_napi {
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struct napi_struct napi ____cacheline_aligned;
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struct ena_ring *tx_ring;
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struct ena_ring *rx_ring;
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u32 qid;
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struct dim dim;
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};
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struct ena_calc_queue_size_ctx {
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struct ena_com_dev_get_features_ctx *get_feat_ctx;
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struct ena_com_dev *ena_dev;
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struct pci_dev *pdev;
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u16 tx_queue_size;
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u16 rx_queue_size;
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u16 max_tx_queue_size;
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u16 max_rx_queue_size;
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u16 max_tx_sgl_size;
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u16 max_rx_sgl_size;
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};
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struct ena_tx_buffer {
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struct sk_buff *skb;
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/* num of ena desc for this specific skb
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* (includes data desc and metadata desc)
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*/
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u32 tx_descs;
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/* num of buffers used by this skb */
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u32 num_of_bufs;
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/* Indicate if bufs[0] map the linear data of the skb. */
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u8 map_linear_data;
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/* Used for detect missing tx packets to limit the number of prints */
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u32 print_once;
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/* Save the last jiffies to detect missing tx packets
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*
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* sets to non zero value on ena_start_xmit and set to zero on
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* napi and timer_Service_routine.
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*
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* while this value is not protected by lock,
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* a given packet is not expected to be handled by ena_start_xmit
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* and by napi/timer_service at the same time.
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*/
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unsigned long last_jiffies;
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struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
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} ____cacheline_aligned;
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struct ena_rx_buffer {
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struct sk_buff *skb;
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struct page *page;
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u32 page_offset;
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struct ena_com_buf ena_buf;
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} ____cacheline_aligned;
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struct ena_stats_tx {
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u64 cnt;
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u64 bytes;
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u64 queue_stop;
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u64 prepare_ctx_err;
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u64 queue_wakeup;
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u64 dma_mapping_err;
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u64 linearize;
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u64 linearize_failed;
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u64 napi_comp;
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u64 tx_poll;
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u64 doorbells;
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u64 bad_req_id;
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u64 llq_buffer_copy;
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u64 missed_tx;
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};
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struct ena_stats_rx {
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u64 cnt;
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u64 bytes;
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u64 rx_copybreak_pkt;
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u64 csum_good;
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u64 refil_partial;
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u64 bad_csum;
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u64 page_alloc_fail;
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u64 skb_alloc_fail;
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u64 dma_mapping_err;
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u64 bad_desc_num;
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u64 bad_req_id;
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u64 empty_rx_ring;
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u64 csum_unchecked;
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};
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struct ena_ring {
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/* Holds the empty requests for TX/RX
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* out of order completions
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*/
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u16 *free_ids;
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union {
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struct ena_tx_buffer *tx_buffer_info;
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struct ena_rx_buffer *rx_buffer_info;
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};
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/* cache ptr to avoid using the adapter */
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struct device *dev;
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struct pci_dev *pdev;
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struct napi_struct *napi;
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struct net_device *netdev;
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struct ena_com_dev *ena_dev;
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struct ena_adapter *adapter;
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struct ena_com_io_cq *ena_com_io_cq;
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struct ena_com_io_sq *ena_com_io_sq;
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u16 next_to_use;
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u16 next_to_clean;
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u16 rx_copybreak;
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u16 qid;
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u16 mtu;
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u16 sgl_size;
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/* The maximum header length the device can handle */
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u8 tx_max_header_size;
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bool first_interrupt;
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u16 no_interrupt_event_cnt;
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/* cpu for TPH */
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int cpu;
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/* number of tx/rx_buffer_info's entries */
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int ring_size;
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enum ena_admin_placement_policy_type tx_mem_queue_type;
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struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS];
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u32 smoothed_interval;
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u32 per_napi_packets;
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u16 non_empty_napi_events;
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struct u64_stats_sync syncp;
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union {
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struct ena_stats_tx tx_stats;
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struct ena_stats_rx rx_stats;
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};
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u8 *push_buf_intermediate_buf;
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int empty_rx_queue;
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} ____cacheline_aligned;
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struct ena_stats_dev {
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u64 tx_timeout;
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u64 suspend;
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u64 resume;
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u64 wd_expired;
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u64 interface_up;
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u64 interface_down;
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u64 admin_q_pause;
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u64 rx_drops;
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};
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enum ena_flags_t {
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ENA_FLAG_DEVICE_RUNNING,
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ENA_FLAG_DEV_UP,
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ENA_FLAG_LINK_UP,
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ENA_FLAG_MSIX_ENABLED,
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ENA_FLAG_TRIGGER_RESET,
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ENA_FLAG_ONGOING_RESET
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};
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/* adapter specific private data structure */
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struct ena_adapter {
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struct ena_com_dev *ena_dev;
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/* OS defined structs */
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struct net_device *netdev;
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struct pci_dev *pdev;
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/* rx packets that shorter that this len will be copied to the skb
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* header
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*/
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u32 rx_copybreak;
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u32 max_mtu;
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int num_queues;
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int msix_vecs;
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u32 missing_tx_completion_threshold;
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u32 requested_tx_ring_size;
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u32 requested_rx_ring_size;
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u32 max_tx_ring_size;
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u32 max_rx_ring_size;
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u32 msg_enable;
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u16 max_tx_sgl_size;
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u16 max_rx_sgl_size;
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u8 mac_addr[ETH_ALEN];
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unsigned long keep_alive_timeout;
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unsigned long missing_tx_completion_to;
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char name[ENA_NAME_MAX_LEN];
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unsigned long flags;
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/* TX */
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struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES]
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____cacheline_aligned_in_smp;
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/* RX */
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struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES]
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____cacheline_aligned_in_smp;
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struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES];
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struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)];
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/* timer service */
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struct work_struct reset_task;
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struct timer_list timer_service;
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bool wd_state;
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bool dev_up_before_reset;
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unsigned long last_keep_alive_jiffies;
|
||
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|
||
|
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struct u64_stats_sync syncp;
|
||
|
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struct ena_stats_dev dev_stats;
|
||
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|
|
||
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|
/* last queue index that was checked for uncompleted tx packets */
|
||
|
|
u32 last_monitored_tx_qid;
|
||
|
|
|
||
|
|
enum ena_regs_reset_reason_types reset_reason;
|
||
|
|
};
|
||
|
|
|
||
|
|
void ena_set_ethtool_ops(struct net_device *netdev);
|
||
|
|
|
||
|
|
void ena_dump_stats_to_dmesg(struct ena_adapter *adapter);
|
||
|
|
|
||
|
|
void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
|
||
|
|
|
||
|
|
int ena_update_queue_sizes(struct ena_adapter *adapter,
|
||
|
|
u32 new_tx_size,
|
||
|
|
u32 new_rx_size);
|
||
|
|
|
||
|
|
int ena_get_sset_count(struct net_device *netdev, int sset);
|
||
|
|
|
||
|
|
#endif /* !(ENA_H) */
|