644 lines
19 KiB
C
644 lines
19 KiB
C
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// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2016-2018, NXP Semiconductors
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* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
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* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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#include <linux/spi/spi.h>
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#include <linux/packing.h>
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#include "sja1105.h"
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#define SJA1105_SIZE_PORT_CTRL 4
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#define SJA1105_SIZE_RESET_CMD 4
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#define SJA1105_SIZE_SPI_MSG_HEADER 4
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#define SJA1105_SIZE_SPI_MSG_MAXLEN (64 * 4)
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#define SJA1105_SIZE_SPI_TRANSFER_MAX \
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(SJA1105_SIZE_SPI_MSG_HEADER + SJA1105_SIZE_SPI_MSG_MAXLEN)
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static int sja1105_spi_transfer(const struct sja1105_private *priv,
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const void *tx, void *rx, int size)
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{
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struct spi_device *spi = priv->spidev;
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struct spi_transfer transfer = {
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.tx_buf = tx,
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.rx_buf = rx,
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.len = size,
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};
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struct spi_message msg;
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int rc;
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if (size > SJA1105_SIZE_SPI_TRANSFER_MAX) {
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dev_err(&spi->dev, "SPI message (%d) longer than max of %d\n",
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size, SJA1105_SIZE_SPI_TRANSFER_MAX);
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return -EMSGSIZE;
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}
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spi_message_init(&msg);
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spi_message_add_tail(&transfer, &msg);
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rc = spi_sync(spi, &msg);
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if (rc < 0) {
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dev_err(&spi->dev, "SPI transfer failed: %d\n", rc);
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return rc;
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}
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return rc;
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}
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static void
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sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg)
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{
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const int size = SJA1105_SIZE_SPI_MSG_HEADER;
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memset(buf, 0, size);
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sja1105_pack(buf, &msg->access, 31, 31, size);
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sja1105_pack(buf, &msg->read_count, 30, 25, size);
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sja1105_pack(buf, &msg->address, 24, 4, size);
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}
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/* If @rw is:
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* - SPI_WRITE: creates and sends an SPI write message at absolute
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* address reg_addr, taking size_bytes from *packed_buf
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* - SPI_READ: creates and sends an SPI read message from absolute
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* address reg_addr, writing size_bytes into *packed_buf
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*
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* This function should only be called if it is priorly known that
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* @size_bytes is smaller than SIZE_SPI_MSG_MAXLEN. Larger packed buffers
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* are chunked in smaller pieces by sja1105_spi_send_long_packed_buf below.
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*/
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int sja1105_spi_send_packed_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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void *packed_buf, size_t size_bytes)
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{
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u8 tx_buf[SJA1105_SIZE_SPI_TRANSFER_MAX] = {0};
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u8 rx_buf[SJA1105_SIZE_SPI_TRANSFER_MAX] = {0};
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const int msg_len = size_bytes + SJA1105_SIZE_SPI_MSG_HEADER;
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struct sja1105_spi_message msg = {0};
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int rc;
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if (msg_len > SJA1105_SIZE_SPI_TRANSFER_MAX)
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return -ERANGE;
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msg.access = rw;
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msg.address = reg_addr;
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if (rw == SPI_READ)
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msg.read_count = size_bytes / 4;
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sja1105_spi_message_pack(tx_buf, &msg);
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if (rw == SPI_WRITE)
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memcpy(tx_buf + SJA1105_SIZE_SPI_MSG_HEADER,
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packed_buf, size_bytes);
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rc = sja1105_spi_transfer(priv, tx_buf, rx_buf, msg_len);
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if (rc < 0)
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return rc;
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if (rw == SPI_READ)
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memcpy(packed_buf, rx_buf + SJA1105_SIZE_SPI_MSG_HEADER,
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size_bytes);
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return 0;
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}
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/* If @rw is:
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* - SPI_WRITE: creates and sends an SPI write message at absolute
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* address reg_addr, taking size_bytes from *packed_buf
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* - SPI_READ: creates and sends an SPI read message from absolute
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* address reg_addr, writing size_bytes into *packed_buf
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*
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* The u64 *value is unpacked, meaning that it's stored in the native
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* CPU endianness and directly usable by software running on the core.
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*
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* This is a wrapper around sja1105_spi_send_packed_buf().
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*/
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int sja1105_spi_send_int(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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u64 *value, u64 size_bytes)
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{
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u8 packed_buf[SJA1105_SIZE_SPI_MSG_MAXLEN];
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int rc;
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if (size_bytes > SJA1105_SIZE_SPI_MSG_MAXLEN)
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return -ERANGE;
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if (rw == SPI_WRITE)
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sja1105_pack(packed_buf, value, 8 * size_bytes - 1, 0,
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size_bytes);
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rc = sja1105_spi_send_packed_buf(priv, rw, reg_addr, packed_buf,
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size_bytes);
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if (rw == SPI_READ)
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sja1105_unpack(packed_buf, value, 8 * size_bytes - 1, 0,
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size_bytes);
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return rc;
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}
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/* Should be used if a @packed_buf larger than SJA1105_SIZE_SPI_MSG_MAXLEN
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* must be sent/received. Splitting the buffer into chunks and assembling
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* those into SPI messages is done automatically by this function.
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*/
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int sja1105_spi_send_long_packed_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 base_addr,
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void *packed_buf, u64 buf_len)
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{
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struct chunk {
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void *buf_ptr;
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int len;
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u64 spi_address;
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} chunk;
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int distance_to_end;
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int rc;
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/* Initialize chunk */
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chunk.buf_ptr = packed_buf;
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chunk.spi_address = base_addr;
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chunk.len = min_t(int, buf_len, SJA1105_SIZE_SPI_MSG_MAXLEN);
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while (chunk.len) {
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rc = sja1105_spi_send_packed_buf(priv, rw, chunk.spi_address,
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chunk.buf_ptr, chunk.len);
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if (rc < 0)
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return rc;
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chunk.buf_ptr += chunk.len;
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chunk.spi_address += chunk.len / 4;
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distance_to_end = (uintptr_t)(packed_buf + buf_len -
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chunk.buf_ptr);
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chunk.len = min(distance_to_end, SJA1105_SIZE_SPI_MSG_MAXLEN);
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}
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return 0;
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}
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/* Back-ported structure from UM11040 Table 112.
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* Reset control register (addr. 100440h)
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* In the SJA1105 E/T, only warm_rst and cold_rst are
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* supported (exposed in UM10944 as rst_ctrl), but the bit
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* offsets of warm_rst and cold_rst are actually reversed.
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*/
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struct sja1105_reset_cmd {
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u64 switch_rst;
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u64 cfg_rst;
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u64 car_rst;
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u64 otp_rst;
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u64 warm_rst;
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u64 cold_rst;
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u64 por_rst;
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};
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static void
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sja1105et_reset_cmd_pack(void *buf, const struct sja1105_reset_cmd *reset)
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{
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const int size = SJA1105_SIZE_RESET_CMD;
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memset(buf, 0, size);
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sja1105_pack(buf, &reset->cold_rst, 3, 3, size);
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sja1105_pack(buf, &reset->warm_rst, 2, 2, size);
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}
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static void
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sja1105pqrs_reset_cmd_pack(void *buf, const struct sja1105_reset_cmd *reset)
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{
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const int size = SJA1105_SIZE_RESET_CMD;
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memset(buf, 0, size);
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sja1105_pack(buf, &reset->switch_rst, 8, 8, size);
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sja1105_pack(buf, &reset->cfg_rst, 7, 7, size);
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sja1105_pack(buf, &reset->car_rst, 5, 5, size);
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sja1105_pack(buf, &reset->otp_rst, 4, 4, size);
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sja1105_pack(buf, &reset->warm_rst, 3, 3, size);
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sja1105_pack(buf, &reset->cold_rst, 2, 2, size);
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sja1105_pack(buf, &reset->por_rst, 1, 1, size);
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}
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static int sja1105et_reset_cmd(const void *ctx, const void *data)
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{
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const struct sja1105_private *priv = ctx;
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const struct sja1105_reset_cmd *reset = data;
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const struct sja1105_regs *regs = priv->info->regs;
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struct device *dev = priv->ds->dev;
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u8 packed_buf[SJA1105_SIZE_RESET_CMD];
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if (reset->switch_rst ||
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reset->cfg_rst ||
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reset->car_rst ||
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reset->otp_rst ||
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reset->por_rst) {
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dev_err(dev, "Only warm and cold reset is supported "
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"for SJA1105 E/T!\n");
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return -EINVAL;
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}
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if (reset->warm_rst)
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dev_dbg(dev, "Warm reset requested\n");
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if (reset->cold_rst)
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dev_dbg(dev, "Cold reset requested\n");
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sja1105et_reset_cmd_pack(packed_buf, reset);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rgu,
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packed_buf, SJA1105_SIZE_RESET_CMD);
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}
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static int sja1105pqrs_reset_cmd(const void *ctx, const void *data)
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{
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const struct sja1105_private *priv = ctx;
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const struct sja1105_reset_cmd *reset = data;
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const struct sja1105_regs *regs = priv->info->regs;
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struct device *dev = priv->ds->dev;
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u8 packed_buf[SJA1105_SIZE_RESET_CMD];
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if (reset->switch_rst)
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dev_dbg(dev, "Main reset for all functional modules requested\n");
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if (reset->cfg_rst)
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dev_dbg(dev, "Chip configuration reset requested\n");
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if (reset->car_rst)
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dev_dbg(dev, "Clock and reset control logic reset requested\n");
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if (reset->otp_rst)
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dev_dbg(dev, "OTP read cycle for reading product "
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"config settings requested\n");
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if (reset->warm_rst)
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dev_dbg(dev, "Warm reset requested\n");
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if (reset->cold_rst)
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dev_dbg(dev, "Cold reset requested\n");
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if (reset->por_rst)
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dev_dbg(dev, "Power-on reset requested\n");
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sja1105pqrs_reset_cmd_pack(packed_buf, reset);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rgu,
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packed_buf, SJA1105_SIZE_RESET_CMD);
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}
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static int sja1105_cold_reset(const struct sja1105_private *priv)
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{
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struct sja1105_reset_cmd reset = {0};
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reset.cold_rst = 1;
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return priv->info->reset_cmd(priv, &reset);
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}
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int sja1105_inhibit_tx(const struct sja1105_private *priv,
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unsigned long port_bitmap, bool tx_inhibited)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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u64 inhibit_cmd;
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int rc;
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rc = sja1105_spi_send_int(priv, SPI_READ, regs->port_control,
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&inhibit_cmd, SJA1105_SIZE_PORT_CTRL);
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if (rc < 0)
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return rc;
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if (tx_inhibited)
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inhibit_cmd |= port_bitmap;
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else
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inhibit_cmd &= ~port_bitmap;
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return sja1105_spi_send_int(priv, SPI_WRITE, regs->port_control,
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&inhibit_cmd, SJA1105_SIZE_PORT_CTRL);
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}
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struct sja1105_status {
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u64 configs;
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u64 crcchkl;
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u64 ids;
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u64 crcchkg;
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};
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/* This is not reading the entire General Status area, which is also
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* divergent between E/T and P/Q/R/S, but only the relevant bits for
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* ensuring that the static config upload procedure was successful.
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*/
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static void sja1105_status_unpack(void *buf, struct sja1105_status *status)
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{
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/* So that addition translates to 4 bytes */
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u32 *p = buf;
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/* device_id is missing from the buffer, but we don't
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* want to diverge from the manual definition of the
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* register addresses, so we'll back off one step with
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* the register pointer, and never access p[0].
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*/
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p--;
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sja1105_unpack(p + 0x1, &status->configs, 31, 31, 4);
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sja1105_unpack(p + 0x1, &status->crcchkl, 30, 30, 4);
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sja1105_unpack(p + 0x1, &status->ids, 29, 29, 4);
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sja1105_unpack(p + 0x1, &status->crcchkg, 28, 28, 4);
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}
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static int sja1105_status_get(struct sja1105_private *priv,
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struct sja1105_status *status)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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u8 packed_buf[4];
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int rc;
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rc = sja1105_spi_send_packed_buf(priv, SPI_READ,
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regs->status,
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packed_buf, 4);
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if (rc < 0)
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return rc;
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sja1105_status_unpack(packed_buf, status);
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return 0;
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}
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|
||
|
|
/* Not const because unpacking priv->static_config into buffers and preparing
|
||
|
|
* for upload requires the recalculation of table CRCs and updating the
|
||
|
|
* structures with these.
|
||
|
|
*/
|
||
|
|
static int
|
||
|
|
static_config_buf_prepare_for_upload(struct sja1105_private *priv,
|
||
|
|
void *config_buf, int buf_len)
|
||
|
|
{
|
||
|
|
struct sja1105_static_config *config = &priv->static_config;
|
||
|
|
struct sja1105_table_header final_header;
|
||
|
|
sja1105_config_valid_t valid;
|
||
|
|
char *final_header_ptr;
|
||
|
|
int crc_len;
|
||
|
|
|
||
|
|
valid = sja1105_static_config_check_valid(config);
|
||
|
|
if (valid != SJA1105_CONFIG_OK) {
|
||
|
|
dev_err(&priv->spidev->dev,
|
||
|
|
sja1105_static_config_error_msg[valid]);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Write Device ID and config tables to config_buf */
|
||
|
|
sja1105_static_config_pack(config_buf, config);
|
||
|
|
/* Recalculate CRC of the last header (right now 0xDEADBEEF).
|
||
|
|
* Don't include the CRC field itself.
|
||
|
|
*/
|
||
|
|
crc_len = buf_len - 4;
|
||
|
|
/* Read the whole table header */
|
||
|
|
final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER;
|
||
|
|
sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK);
|
||
|
|
/* Modify */
|
||
|
|
final_header.crc = sja1105_crc32(config_buf, crc_len);
|
||
|
|
/* Rewrite */
|
||
|
|
sja1105_table_header_packing(final_header_ptr, &final_header, PACK);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#define RETRIES 10
|
||
|
|
|
||
|
|
int sja1105_static_config_upload(struct sja1105_private *priv)
|
||
|
|
{
|
||
|
|
unsigned long port_bitmap = GENMASK_ULL(SJA1105_NUM_PORTS - 1, 0);
|
||
|
|
struct sja1105_static_config *config = &priv->static_config;
|
||
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
||
|
|
struct device *dev = &priv->spidev->dev;
|
||
|
|
struct sja1105_status status;
|
||
|
|
int rc, retries = RETRIES;
|
||
|
|
u8 *config_buf;
|
||
|
|
int buf_len;
|
||
|
|
|
||
|
|
buf_len = sja1105_static_config_get_length(config);
|
||
|
|
config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL);
|
||
|
|
if (!config_buf)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len);
|
||
|
|
if (rc < 0) {
|
||
|
|
dev_err(dev, "Invalid config, cannot upload\n");
|
||
|
|
rc = -EINVAL;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
/* Prevent PHY jabbering during switch reset by inhibiting
|
||
|
|
* Tx on all ports and waiting for current packet to drain.
|
||
|
|
* Otherwise, the PHY will see an unterminated Ethernet packet.
|
||
|
|
*/
|
||
|
|
rc = sja1105_inhibit_tx(priv, port_bitmap, true);
|
||
|
|
if (rc < 0) {
|
||
|
|
dev_err(dev, "Failed to inhibit Tx on ports\n");
|
||
|
|
rc = -ENXIO;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
/* Wait for an eventual egress packet to finish transmission
|
||
|
|
* (reach IFG). It is guaranteed that a second one will not
|
||
|
|
* follow, and that switch cold reset is thus safe
|
||
|
|
*/
|
||
|
|
usleep_range(500, 1000);
|
||
|
|
do {
|
||
|
|
/* Put the SJA1105 in programming mode */
|
||
|
|
rc = sja1105_cold_reset(priv);
|
||
|
|
if (rc < 0) {
|
||
|
|
dev_err(dev, "Failed to reset switch, retrying...\n");
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
/* Wait for the switch to come out of reset */
|
||
|
|
usleep_range(1000, 5000);
|
||
|
|
/* Upload the static config to the device */
|
||
|
|
rc = sja1105_spi_send_long_packed_buf(priv, SPI_WRITE,
|
||
|
|
regs->config,
|
||
|
|
config_buf, buf_len);
|
||
|
|
if (rc < 0) {
|
||
|
|
dev_err(dev, "Failed to upload config, retrying...\n");
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
/* Check that SJA1105 responded well to the config upload */
|
||
|
|
rc = sja1105_status_get(priv, &status);
|
||
|
|
if (rc < 0)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (status.ids == 1) {
|
||
|
|
dev_err(dev, "Mismatch between hardware and static config "
|
||
|
|
"device id. Wrote 0x%llx, wants 0x%llx\n",
|
||
|
|
config->device_id, priv->info->device_id);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
if (status.crcchkl == 1) {
|
||
|
|
dev_err(dev, "Switch reported invalid local CRC on "
|
||
|
|
"the uploaded config, retrying...\n");
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
if (status.crcchkg == 1) {
|
||
|
|
dev_err(dev, "Switch reported invalid global CRC on "
|
||
|
|
"the uploaded config, retrying...\n");
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
if (status.configs == 0) {
|
||
|
|
dev_err(dev, "Switch reported that configuration is "
|
||
|
|
"invalid, retrying...\n");
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
/* Success! */
|
||
|
|
break;
|
||
|
|
} while (--retries);
|
||
|
|
|
||
|
|
if (!retries) {
|
||
|
|
rc = -EIO;
|
||
|
|
dev_err(dev, "Failed to upload config to device, giving up\n");
|
||
|
|
goto out;
|
||
|
|
} else if (retries != RETRIES) {
|
||
|
|
dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries);
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = sja1105_ptp_reset(priv);
|
||
|
|
if (rc < 0)
|
||
|
|
dev_err(dev, "Failed to reset PTP clock: %d\n", rc);
|
||
|
|
|
||
|
|
dev_info(dev, "Reset switch and programmed static config\n");
|
||
|
|
|
||
|
|
out:
|
||
|
|
kfree(config_buf);
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct sja1105_regs sja1105et_regs = {
|
||
|
|
.device_id = 0x0,
|
||
|
|
.prod_id = 0x100BC3,
|
||
|
|
.status = 0x1,
|
||
|
|
.port_control = 0x11,
|
||
|
|
.config = 0x020000,
|
||
|
|
.rgu = 0x100440,
|
||
|
|
/* UM10944.pdf, Table 86, ACU Register overview */
|
||
|
|
.pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
|
||
|
|
.rmii_pll1 = 0x10000A,
|
||
|
|
.cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
|
||
|
|
.mac = {0x200, 0x202, 0x204, 0x206, 0x208},
|
||
|
|
.mac_hl1 = {0x400, 0x410, 0x420, 0x430, 0x440},
|
||
|
|
.mac_hl2 = {0x600, 0x610, 0x620, 0x630, 0x640},
|
||
|
|
/* UM10944.pdf, Table 78, CGU Register overview */
|
||
|
|
.mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F},
|
||
|
|
.mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030},
|
||
|
|
.mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
|
||
|
|
.mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035},
|
||
|
|
.rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032},
|
||
|
|
.rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031},
|
||
|
|
.rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
|
||
|
|
.ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8},
|
||
|
|
.ptp_control = 0x17,
|
||
|
|
.ptpclk = 0x18, /* Spans 0x18 to 0x19 */
|
||
|
|
.ptpclkrate = 0x1A,
|
||
|
|
.ptptsclk = 0x1B, /* Spans 0x1B to 0x1C */
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct sja1105_regs sja1105pqrs_regs = {
|
||
|
|
.device_id = 0x0,
|
||
|
|
.prod_id = 0x100BC3,
|
||
|
|
.status = 0x1,
|
||
|
|
.port_control = 0x12,
|
||
|
|
.config = 0x020000,
|
||
|
|
.rgu = 0x100440,
|
||
|
|
/* UM10944.pdf, Table 86, ACU Register overview */
|
||
|
|
.pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
|
||
|
|
.pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814},
|
||
|
|
.rmii_pll1 = 0x10000A,
|
||
|
|
.cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
|
||
|
|
.mac = {0x200, 0x202, 0x204, 0x206, 0x208},
|
||
|
|
.mac_hl1 = {0x400, 0x410, 0x420, 0x430, 0x440},
|
||
|
|
.mac_hl2 = {0x600, 0x610, 0x620, 0x630, 0x640},
|
||
|
|
/* UM11040.pdf, Table 114 */
|
||
|
|
.mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B},
|
||
|
|
.mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C},
|
||
|
|
.mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
|
||
|
|
.mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030},
|
||
|
|
.rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E},
|
||
|
|
.rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D},
|
||
|
|
.rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
|
||
|
|
.qlevel = {0x604, 0x614, 0x624, 0x634, 0x644},
|
||
|
|
.ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0},
|
||
|
|
.ptp_control = 0x18,
|
||
|
|
.ptpclk = 0x19,
|
||
|
|
.ptpclkrate = 0x1B,
|
||
|
|
.ptptsclk = 0x1C,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct sja1105_info sja1105e_info = {
|
||
|
|
.device_id = SJA1105E_DEVICE_ID,
|
||
|
|
.part_no = SJA1105ET_PART_NO,
|
||
|
|
.static_ops = sja1105e_table_ops,
|
||
|
|
.dyn_ops = sja1105et_dyn_ops,
|
||
|
|
.ptp_ts_bits = 24,
|
||
|
|
.ptpegr_ts_bytes = 4,
|
||
|
|
.reset_cmd = sja1105et_reset_cmd,
|
||
|
|
.fdb_add_cmd = sja1105et_fdb_add,
|
||
|
|
.fdb_del_cmd = sja1105et_fdb_del,
|
||
|
|
.ptp_cmd = sja1105et_ptp_cmd,
|
||
|
|
.regs = &sja1105et_regs,
|
||
|
|
.name = "SJA1105E",
|
||
|
|
};
|
||
|
|
struct sja1105_info sja1105t_info = {
|
||
|
|
.device_id = SJA1105T_DEVICE_ID,
|
||
|
|
.part_no = SJA1105ET_PART_NO,
|
||
|
|
.static_ops = sja1105t_table_ops,
|
||
|
|
.dyn_ops = sja1105et_dyn_ops,
|
||
|
|
.ptp_ts_bits = 24,
|
||
|
|
.ptpegr_ts_bytes = 4,
|
||
|
|
.reset_cmd = sja1105et_reset_cmd,
|
||
|
|
.fdb_add_cmd = sja1105et_fdb_add,
|
||
|
|
.fdb_del_cmd = sja1105et_fdb_del,
|
||
|
|
.ptp_cmd = sja1105et_ptp_cmd,
|
||
|
|
.regs = &sja1105et_regs,
|
||
|
|
.name = "SJA1105T",
|
||
|
|
};
|
||
|
|
struct sja1105_info sja1105p_info = {
|
||
|
|
.device_id = SJA1105PR_DEVICE_ID,
|
||
|
|
.part_no = SJA1105P_PART_NO,
|
||
|
|
.static_ops = sja1105p_table_ops,
|
||
|
|
.dyn_ops = sja1105pqrs_dyn_ops,
|
||
|
|
.ptp_ts_bits = 32,
|
||
|
|
.ptpegr_ts_bytes = 8,
|
||
|
|
.setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
|
||
|
|
.reset_cmd = sja1105pqrs_reset_cmd,
|
||
|
|
.fdb_add_cmd = sja1105pqrs_fdb_add,
|
||
|
|
.fdb_del_cmd = sja1105pqrs_fdb_del,
|
||
|
|
.ptp_cmd = sja1105pqrs_ptp_cmd,
|
||
|
|
.regs = &sja1105pqrs_regs,
|
||
|
|
.name = "SJA1105P",
|
||
|
|
};
|
||
|
|
struct sja1105_info sja1105q_info = {
|
||
|
|
.device_id = SJA1105QS_DEVICE_ID,
|
||
|
|
.part_no = SJA1105Q_PART_NO,
|
||
|
|
.static_ops = sja1105q_table_ops,
|
||
|
|
.dyn_ops = sja1105pqrs_dyn_ops,
|
||
|
|
.ptp_ts_bits = 32,
|
||
|
|
.ptpegr_ts_bytes = 8,
|
||
|
|
.setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
|
||
|
|
.reset_cmd = sja1105pqrs_reset_cmd,
|
||
|
|
.fdb_add_cmd = sja1105pqrs_fdb_add,
|
||
|
|
.fdb_del_cmd = sja1105pqrs_fdb_del,
|
||
|
|
.ptp_cmd = sja1105pqrs_ptp_cmd,
|
||
|
|
.regs = &sja1105pqrs_regs,
|
||
|
|
.name = "SJA1105Q",
|
||
|
|
};
|
||
|
|
struct sja1105_info sja1105r_info = {
|
||
|
|
.device_id = SJA1105PR_DEVICE_ID,
|
||
|
|
.part_no = SJA1105R_PART_NO,
|
||
|
|
.static_ops = sja1105r_table_ops,
|
||
|
|
.dyn_ops = sja1105pqrs_dyn_ops,
|
||
|
|
.ptp_ts_bits = 32,
|
||
|
|
.ptpegr_ts_bytes = 8,
|
||
|
|
.setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
|
||
|
|
.reset_cmd = sja1105pqrs_reset_cmd,
|
||
|
|
.fdb_add_cmd = sja1105pqrs_fdb_add,
|
||
|
|
.fdb_del_cmd = sja1105pqrs_fdb_del,
|
||
|
|
.ptp_cmd = sja1105pqrs_ptp_cmd,
|
||
|
|
.regs = &sja1105pqrs_regs,
|
||
|
|
.name = "SJA1105R",
|
||
|
|
};
|
||
|
|
struct sja1105_info sja1105s_info = {
|
||
|
|
.device_id = SJA1105QS_DEVICE_ID,
|
||
|
|
.part_no = SJA1105S_PART_NO,
|
||
|
|
.static_ops = sja1105s_table_ops,
|
||
|
|
.dyn_ops = sja1105pqrs_dyn_ops,
|
||
|
|
.regs = &sja1105pqrs_regs,
|
||
|
|
.ptp_ts_bits = 32,
|
||
|
|
.ptpegr_ts_bytes = 8,
|
||
|
|
.setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
|
||
|
|
.reset_cmd = sja1105pqrs_reset_cmd,
|
||
|
|
.fdb_add_cmd = sja1105pqrs_fdb_add,
|
||
|
|
.fdb_del_cmd = sja1105pqrs_fdb_del,
|
||
|
|
.ptp_cmd = sja1105pqrs_ptp_cmd,
|
||
|
|
.name = "SJA1105S",
|
||
|
|
};
|